Z16F2810VH20SG Zilog, Z16F2810VH20SG Datasheet - Page 212

• Manufacturer Part Number: Z16F2810VH20SG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4536

®
ZNEO
Z16F Series
Product Specification
196
is detected in the Slave by SS changing state. The SS framing signal will lead the frame by
one SCK period. In this mode SCK will run continuously, starting with the initial SS
assertion. Frames will run back-to-back as long as software/DMA continue to provide
2
data. The I
S protocol (Inter IC Sound) is used to carry left and right channel audio data
with the SS signal indicating which channel is being sent. In Slave mode, the change in
state of SS (Low to High or High to Low) will trigger the start of a transaction on the next
SCK cycle.
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. For information
on valid bit positions when the character length is less than 8-bits, see
ESPI Data Register
description on page 191.
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits
SSIO—Slave Select I/O
This bit controls the direction of the SS pin. In single Master mode, SSIO is set to 1 unless
a separate GPIO pin is being used to provide the SS output function. In the SPI Slave or
Multi-Master configuration SSIO is set to 0.
0 = SS pin configured as an input (SPI Slave and Multi-Master modes)
1 = SS pin configured as an output (SPI single Master mode)
SSPO—Slave Select Polarity
This bit controls the polarity of the SS pin.
0 = SS is active Low. (SSV = 1 corresponds to SS = 0)
1 = SS is active High. (SSV = 1 corresponds to SS = 1)
PS022008-0810
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface