Z16F2810VH20SG Zilog, Z16F2810VH20SG Datasheet - Page 288

• Manufacturer Part Number: Z16F2810VH20SG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4536

®
ZNEO
Z16F Series
Product Specification
272
increment or decrement. In quad mode, the transfer length is still decremented by one.
This allows 64 Kquads to be transferred.
DSTCTL and SRCCTL Fields
The DSTCTL and SRCCTL fields control the increment or decrement of the source and
destination addresses. The address is set to increment, decrement or not change on each
DMA transfer.
00 = Fixed
01 = Increment
10 = Decrement
11 = Reserved
IEOB (Interrupt on End Of Buffer)
The Interrupt on end of buffer bit forces the DMA channel to generate an interrupt when
the buffer is closed. If the DMA is operating in direct mode and the TXLN decrements to
on page 273) and this bit is set then a 
the watermark value (See
DMA Water Mark
interrupt is also generated.
TXFR (Transfer List)
If the DMA is operating in linked list mode and this bit is set, the DMA uses the next LAR
address in the descriptor for the next descriptor address instead of incrementing the current
DMAxLAR address by 16. This allows looping, true linked lists with buffers following
the descriptor or just transfers to other loops.
EOF (End of Frame)
If this bit is set, the EOF signal is sent to the peripheral on the last transfer in the buffer
(that is TXLN == 1). This signals the peripheral to close this frame. This is only used for
on chip peripherals. This bit is also set if a peripheral requests an end of frame before the
buffer transfer is completed.
HALT (Halt after this buffer)
If this bit is set then the DMA stops after this buffer is closed. The DMAxLAR points to
the next descriptor but the descriptor will not be fetched.
CMDSTAT (Command Status)
These four bits are exported to the requesting device on the CMDBUS on the first transfer
of a new buffer. These bits are set by a software write or from the DMA reading the
descriptor. At the end of a buffer these four bits will contain status from the peripheral if
the EOF bit is set. See peripheral devices specs for definitions of commands and status.
PS022008-0810
P R E L I M I N A R Y
DMA Controller