MCL908QY2CDTE Freescale Semiconductor, MCL908QY2CDTE Datasheet
MCL908QY2CDTE
Specifications of MCL908QY2CDTE
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MCL908QY2CDTE Summary of contents
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MC68HLC908QY4 MC68HLC908QT4 MC68HLC908QY2 MC68HLC908QT2 MC68HLC908QY1 MC68HLC908QT1 Data Sheet M68HC08 Microcontrollers MC68HLC908QY4/D Rev. 3 07/2005 freescale.com ...
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...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004. All rights reserved. ...
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... TIM Status and Control Register 17.3 Package Dimensions 4 Description — In — Clarified SRSR flag setting. — Added information to TSTOP note. — Updated package information. MC68HLC908QY/QT Family Data Sheet, Rev. 3 Number(s) Throughout 7.7 Instruction Set Summary: Freescale Semiconductor Page N 115 154 169 170 ...
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... Chapter 11 Oscillator Module (OSC Chapter 12 Input/Output Ports (PORTS Chapter 13 System Integration Module (SIM 103 Chapter 14 Timer Interface Module (TIM 119 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 163 Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev ...
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... List of Chapters 6 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 Analog-to-Digital Converter (ADC) MC68HLC908QY/QT Family Data Sheet, Rev ...
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... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8 Chapter 4 Auto Wakeup Module (AWU) Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.6 Keyboard Module During Break Interrupts Freescale Semiconductor Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) MC68HLC908QY/QT Family Data Sheet, Rev ...
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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.7 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.8 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.8.1 Oscillator Status Register 11.8.2 Oscillator Trim Register (OSCTRIM Chapter 10 Low-Voltage Inhibit (LVI) Chapter 11 Oscillator Module (OSC) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Freescale Semiconductor Chapter 12 Input/Output Ports (PORTS) Chapter 13 System Integration Module (SIM) MC68HLC908QY/QT Family Data Sheet, Rev ...
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... Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.2.2.4 Break Status Register 139 15.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12 Chapter 14 Timer Interface Module (TIM) Chapter 15 Development Support MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... ADC Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 16.11 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 16.12 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Ordering Information and Mechanical Specifications 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 17.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 17.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Freescale Semiconductor Chapter 16 Electrical Specifications Chapter 17 MC68HLC908QY/QT Family Data Sheet, Rev ...
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... Table of Contents 14 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... FLASH security 1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor 0.4 FLASH Analog-to-Digital Memory Size 1536 bytes ...
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... MC68HLC908QT4, MC68HLC908QT2, and MC68HLC908QT1 are available in these packages: – 8-pin PDIP – 8-pin SOIC – 8-pin dual flat no lead (DFN) package 16 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... MC68HLC908QY4. 1.4 Pin Assignments The MC68HLC908QT4, MC68HLC908QT2, and MC68HLC908QT1 are available in 8-pin packages and the MC68HLC908QY4, MC68HLC908QY2, and MC68HLC908QY1 in 16-pin packages. shows the pin assignment for these packages. Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev. 3 MCU Block Diagram Figure 1-2 17 ...
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... MC68HLC908QT2, AND MC68HLC908QT1: 1536 BYTES USER FLASH DD SS Figure 1-1. Block Diagram MC68HLC908QY/QT Family Data Sheet, Rev. 3 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...
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... PTB6 8 9 PTA5/OSC1/KBI5 16-PIN ASSIGNMENT MC68HC908QY1 TSSOP PTA0/TCH0/KBI0 PTA5/OSC1/KB15 4 5 8-PIN ASSIGNMENT MC68HC908QT1 DFN Freescale Semiconductor V SS PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTA1/TCH1/KBI1 PTA3/RST/KBI3 PTA2/IRQ/KBI2/TCLK MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC V SS PTB0 PTB1 PTA5/OSC1/AD3/KBI5 PTA0/TCH0/KBI0 PTA4/OSC2/AD2/KBI4 PTA1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC ...
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... The PTB pins are not available on the 8-pin packages (see note in 20 Table 1-2. Pin Functions Description 12.1 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Introduction). Freescale Semiconductor Power Power Input Input Input Input Input Input Input Input Input Input Output Output Input ...
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... Pin Name PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 Freescale Semiconductor NOTE Highest-to-Lowest Priority Sequence AD0 → TCH0 → KBI0 → PTA0 AD1 →TCH1 → KBI1 → PTA1 IRQ → KBI2 → TCLK → PTA2 RST → KBI3 → PTA3 OSC2 → AD2 → KBI4 → PTA4 OSC1 → ...
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... General Description 22 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In register figures in this document, reserved locations are marked with the word Reserved or with the letter R. Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev. 3 Figure 2-1 Figure 2-1 and in ...
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... Attempts to execute code from addresses in this range will generate an illegal address reset. (1) (1) Figure 2-1. Memory Map MC68HLC908QY/QT Family Data Sheet, Rev. 3 $2E00 UNIMPLEMENTED 51712 BYTES $F7FF $F800 FLASH MEMORY 1536 BYTES $FDFF MC68HLC908QT1, MC68HLC908QT2, MC68HLC908QY1, and MC68HLC908QY2 Memory Map Freescale Semiconductor ↓ ↓ ...
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... Unimplemented $0003 Unimplemented Read: Data Direction Register A $0004 (DDRA) Write: See page 98. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Figure 2-2, contain most of the control, status, and data registers. Bit AWUL R PTA5 PTA4 Unaffected by reset PTB7 ...
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... RSTEN reset power-on reset (POR) only. = Unimplemented MC68HLC908QY/QT Family Data Sheet, Rev DDRB3 DDRB2 DDRB1 PTAPUE3 PTAPUE2 PTAPUE1 PTBPUE3 PTBPUE2 PTBPUE1 KEYF 0 IMASKK ACKK KBIE3 KBIE2 KBIE1 IRQF 0 IMASK ACK Reserved U = Unaffected Freescale Semiconductor Bit 0 DDRB0 0 PTAPUE0 0 PTBPUE0 0 MODEK 0 KBIE0 0 MODE 0 RSTEN (2) 0 ...
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... Write: See page 133. Reset: Read: TIM Channel 1 Status and $0028 Control Register (TSC1) Write: See page 130. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit COPRS LVISTOP LVIRSTD LVIPWRD One-time writable register after each reset. Exceptions are LVDLVR and LVIRSTD bits. ...
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... Indeterminate after reset ADIV2 ADIV1 ADIV0 Unimplemented MC68HLC908QY/QT Family Data Sheet, Rev Bit 11 Bit 10 Bit 9 Bit 4 Bit 3 Bit 2 Bit ECGON TRIM3 TRIM2 TRIM1 CH4 CH3 CH2 CH1 Bit 4 Bit 3 Bit 2 Bit Reserved U = Unaffected Freescale Semiconductor Bit 0 Bit 8 Bit 0 ECGST 0 TRIM0 0 CH0 1 Bit ...
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... Break Address High $FE09 Register (BRKH) Write: See page 138. Reset: Read: Break Address low $FE0A Register (BRKL) Write: See page 138. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Writing a 0 clears SBSW. POR PIN COP ILOP 1 0 ...
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... BPR5 BPR4 Unaffected by reset TRIM7 TRIM6 TRIM5 TRIM4 Unaffected by reset LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) Unaffected by reset = Unimplemented MC68HLC908QY/QT Family Data Sheet, Rev BPR3 BPR2 BPR1 TRIM3 TRIM2 TRIM1 Reserved U = Unaffected Freescale Semiconductor Bit BPR0 R TRIM0 R ...
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... During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Freescale Semiconductor . Table 2-1. Vector Addresses Vector ...
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... High voltage enabled to array and charge pump High voltage disabled to array and charge pump off 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 32 NOTE HVEN MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 MASS ERASE PGM Freescale Semiconductor ...
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... Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. Freescale Semiconductor NOTE CAUTION MC68HLC908QY/QT Family Data Sheet, Rev ...
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... The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time (1) within the FLASH memory address range. NOTE NOTE CAUTION NOTE (2) . 15.3.2 Security), write to the FLASH block protect register instead maximum. PROG MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... FLBPR or the protected block of FLASH memory is prohibited. Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be erased or programmed only with an external voltage, V allows entry from reset into the monitor mode. Freescale Semiconductor NOTE NOTE PROG NOTE Register ...
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... WAIT FOR A TIME WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, t COMPLETED 9 PROGRAMMING THIS ROW? MC68HLC908QY/QT Family Data Sheet, Rev. 3 NVS PGS PROG CLEAR PGM BIT 11 WAIT FOR A TIME, t NVH 12 CLEAR HVEN BIT 13 WAIT FOR A TIME, t RCV END OF PROGRAMMING Freescale Semiconductor ...
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... Figure 2-6. FLASH Block Protect Start Address Table 2-2. Examples of Protect Start Address BPR[7:0] $00–$B8 $B9 (1011 1001) $BA (1011 1010) $BB (1011 1011) $BC (1011 1100) $DE (1101 1110) $DF (1101 1111) $FE (1111 1110) $FF Freescale Semiconductor BPR6 BPR5 BPR4 BPR3 Unaffected by reset. Initial value from factory is 1. Table 2-2. ...
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... FLASH, or the operation will discontinue and the FLASH will be on standby mode Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. 38 NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return the corresponding DDR bit the DDR bit is 1, the value in the port data latch is read. Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev ...
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... BYTES MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: 1536 BYTES USER FLASH MC68HLC908QY/QT Family Data Sheet, Rev. 3 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...
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... When the input voltage to the ADC equals V voltage equals V the ADC converts it to $00. Input voltages between V SS, linear conversion. All other input voltages will result in $FF if greater than V Input voltage should not exceed the analog supply voltages. Freescale Semiconductor DDRAx RESET PTAx ADC DATA REGISTER ADC VOLTAGE IN ...
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... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before using ADC data after exiting stop mode. 42 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update ADR at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit Continuous ADC conversion 0 = One ADC conversion Freescale Semiconductor ...
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... Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset Figure 3-4. ADC Data Register (ADR) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Input Select PTA0 PTA1 PTA4 PTA5 (1) Unused Reserved Unused (2) V DDA (2) V SSA ADC power off 2 1 Bit 0 Bit 2 Bit 1 Bit 0 Freescale Semiconductor ...
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... MCU operating voltage. Lower operating voltages will require lower ADC clock frequencies for best accuracy. The analog input level should remain stable for the entire conversion time (maximum = 17 ADC clock cycles). ADIV2 don’t care Freescale Semiconductor ADIV1 ADIV0 0 ...
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... Analog-to-Digital Converter (ADC) 46 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... AWUIREQ, is latched and sent to the KBI logic. See Wakeup interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER is set. The AWU shares the keyboard interrupt vector. Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev. 3 Figure 4-1 ...
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... AUTOWUGEN DIV 2 SHORT DIV 2 OVERFLOW CLK RST RESET ACKK RESET ISTOP AWUIE MC68HLC908QY/QT Family Data Sheet, Rev PTA READ, BIT 6 D AWUL Q AWUIREQ KBI INTERRUPT LOGIC (SEE Figure 9-2. Keyboard Interrupt Block Diagram) Figure 4-1) has no effect on AWUL Freescale Semiconductor ...
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... There is no PTA6 port or any of the associated bits such as PTA6 data direction or pullup bits Auto wakeup interrupt request is pending 0 = Auto wakeup interrupt request is not pending PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Freescale Semiconductor AWUL ...
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... Keyboard/auto wakeup interrupt requests not masked MODEK is not used in conjuction with the auto wakeup feature. To see a description of this bit, see KEYF Unimplemented NOTE 9.7.1 Keyboard Status and Control MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Register. Freescale Semiconductor ...
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... This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears AWUIE Auto wakeup enabled as interrupt input 0 = Auto wakeup not enabled as interrupt input KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Register. Freescale Semiconductor AWUIE KBIE5 ...
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... Auto Wakeup Module (AWU) 52 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... The configuration registers are located at $001E and $001F, and may be read at anytime. Address: $001E Bit 7 Read: IRQPUD Write: Reset: 0 POR Reserved R Figure 5-1. Configuration Register 2 (CONFIG2) Freescale Semiconductor IRQEN R OSCOPT1 OSCOPT0 ...
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... LVIRSTD disables the reset signal from the LVI module. Unlike other configuration bits, the LVIRSTD can be written at any time LVI module resets disabled 0 = LVI module resets enabled 54 DD NOTE LVIRSTD LVIPWRD LVDLVR MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 SSREC STOP COPD Freescale Semiconductor ...
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... STOP — STOP Instruction Enable Bit STOP enables the STOP instruction STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module COP module disabled 0 = COP module enabled Freescale Semiconductor NOTE NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 Functional Description 55 ...
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... Configuration Register (CONFIG) 56 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... COPCTL WRITE COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) Freescale Semiconductor 12-BIT SIM COUNTER COP CLOCK 6-BIT COP COUNTER CLEAR COP COUNTER Figure 6-1. COP Block Diagram MC68HLC908QY/QT Family Data Sheet, Rev. 3 ...
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... The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register 58 NOTE NOTE Figure 6.4 COP Control (CONFIG). MC68HLC908QY/QT Family Data Sheet, Rev. 3 13.8.1 SIM Reset Status Register. 6-1. Register) clears the COP Freescale Semiconductor ...
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... COP timeout period after entering or exiting stop mode. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). Freescale Semiconductor (CONFIG ...
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... Computer Operating Properly (COP) 60 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev ...
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... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H:X) MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...
Page 63
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...
Page 64
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HLC908QY/QT Family Data Sheet, Rev Bit Freescale Semiconductor ...
Page 65
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev. 3 Arithmetic/Logic Unit (ALU) ...
Page 66
... REL – – – – – – REL 90 ⊕ – – – – – – REL 92 – – – – – – REL 28 – – – – – – REL 29 – – – – – – REL 22 Freescale Semiconductor ...
Page 67
... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ⊕ ...
Page 68
... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...
Page 69
... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...
Page 70
... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...
Page 71
... M Memory location N Negative bit 7.8 Opcode Map See Table 7-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 72
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 73
... Reset — A reset automatically clears the IRQ latch. The external interrupt pin is falling-edge-triggered out of reset and is software-configurable to be either falling-edge or falling-edge and low-level triggered. The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin. Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev ...
Page 74
... MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: 1536 BYTES USER FLASH DD SS NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...
Page 75
... The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMASK, which makes it useful in applications where polling is preferred. When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. Freescale Semiconductor V DD CLR ...
Page 76
... When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor connected to the IRQ pin; this can be disabled by setting DD the IRQPUD bit in the CONFIG2 register ($001E). 76 Chapter 13 System Integration Module (SIM). NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 77
... IRQ interrupt request disabled 0 = IRQ interrupt request enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only Freescale Semiconductor (CONFIG ...
Page 78
... External Interrupt (IRQ) 78 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 79
... If the keyboard interrupt is falling edge and low-level sensitive, an interrupt request is present as long as any keyboard interrupt input is low. Freescale Semiconductor Register). A logic 0 applied to an enabled keyboard interrupt pin MC68HLC908QY/QT Family Data Sheet, Rev ...
Page 80
... BYTES MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: 1536 BYTES USER FLASH MC68HLC908QY/QT Family Data Sheet, Rev. 3 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...
Page 81
... The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. Freescale Semiconductor V DD CLR ...
Page 82
... To protect the latch during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. 82 NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 83
... Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A and auto wakeup. Reset clears MODEK Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only Freescale Semiconductor ...
Page 84
... KBIx pin not enabled as keyboard interrupt pin AWUIE bit is not used in conjunction with the keyboard interrupt feature. To see a description of this bit, see AWUIE KBIE5 KBIE4 KBIE3 Unimplemented NOTE Chapter 4 Auto Wakeup Module MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 KBIE2 KBIE1 KBIE0 (AWU). Freescale Semiconductor ...
Page 85
... LVI module. LVISTOP, LVIPWRD, LVDLVR, and LVIRSTD are user selectable options found in the configuration register (CONFIG1). See Register (CONFIG LOW V DD DETECTOR LVDLVR FROM CONFIG Freescale Semiconductor voltage falls below the LVI trip falling voltage STOP INSTRUCTION FROM CONFIG LVIRSTD LVIPWRD FROM CONFIG V > LVITRIP = 0 DD ≤ ...
Page 86
... This prevents a condition in which the MCU is TRIPR is approximately equal HYS MC68HLC908QY/QT Family Data Sheet, Rev. 3 voltage. Clearing the LVI DD falls below a voltage, DD for LVD TRIPR for TRIPR rises above a voltage which TRIPR for the reset recovery greater than TRIPF TRIPR Freescale Semiconductor by polling ...
Page 87
... V DD that prevents oscillation into and out of reset (see V 10.5 LVI Interrupts The LVI module does not generate interrupt requests. Freescale Semiconductor application (for example, battery applications). Once LVD DD NOTE [LVD [LVR]) may be lower than this. See TRIPF TRIPF for the actual trip point voltages ...
Page 88
... When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 88 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 89
... The internal oscillator will generate a clock of 4.0 MHz typical (INTCLK) resulting in a bus speed (internal clock ÷ 1.0 MHz. Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and, like the RC oscillator, OSC2 can output BUSCLKX4 by setting OSC2EN in PTAPUE register. See Freescale Semiconductor Chapter 12 Input/Output Ports MC68HLC908QY/QT Family Data Sheet, Rev. 3 (PORTS). 89 ...
Page 90
... BYTES MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: 1536 BYTES USER FLASH MC68HLC908QY/QT Family Data Sheet, Rev. 3 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...
Page 91
... BUSCLKX4 and also divided by two to create BUSCLKX2. In this configuration, the OSC2 pin cannot output BUSCLKX4. So the OSC2EN bit in the port A pullup enable register will be clear to enable PTA4 I/O functions on the pin. Freescale Semiconductor WARNING NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 ...
Page 92
... A pullup enable register can be set to enable the OSC2 output function on the pin. Enabling the OSC2 output slightly increases the external RC oscillator frequency SIM BUSCLKX4 BUSCLKX2 XTALCLK ÷ 2 OSC2 Figure MC68HLC908QY/QT Family Data Sheet, Rev SIM ) to provide a clock source with EXT 11-3. value must have a tolerance of EXT . RCCLK Freescale Semiconductor ...
Page 93
... For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The OSC2EN bit has no effect. For the internal oscillator or RC oscillator options, the OSC2 pin can assume other functions according to Table 1-3. Function Priority in Shared Option XTAL oscillator External clock Internal oscillator or RC oscillator Freescale Semiconductor INTCLK 0 1 EXTERNAL RC RCCLK OSCILLATOR 1 0 OSC1 ...
Page 94
... The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK output, hence BUSCLKX2 and BUSCLKX4. 94 Figure 11-2 shows only the logical relation of XTALCLK to OSC1 shows only the logical relation of RCCLK to OSC1 and may not MC68HLC908QY/QT Family Data Sheet, Rev and comes XCLK 11.3.1.1 Internal Oscillator Freescale Semiconductor ...
Page 95
... External clock generator disabled ECGST — External Clock Status Bit This read-only bit indicates whether or not an external clock source is engaged to drive the system clock external clock source engaged external clock source disengaged Freescale Semiconductor Table 11-2. Oscillator Modes OSCOPT0 Oscillator Modes 0 Internal Oscillator ...
Page 96
... The reset value is $80, which sets the frequency to 4.0 MHz (1.0 MHz bus speed) ±25 TRIM6 TRIM5 TRIM4 TRIM3 MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 TRIM2 TRIM1 TRIM0 Freescale Semiconductor ...
Page 97
... PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. Freescale Semiconductor NOTE (KBI)). Each port A pin also has a software configurable pullup NOTE MC68HLC908QY/QT Family Data Sheet, Rev ...
Page 98
... Figure 12-1. Port A Data Register (PTA) Chapter 4 Auto Wakeup Module DDRA5 DDRA4 DDRA3 Reserved = Unimplemented NOTE MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 PTA2 PTA3 PTA1 PTA0 KBI3 KBI2 KBI1 KBI0 (AWU)). There is no PTA6 Chapter 9 Keyboard Interrupt Module 2 1 Bit 0 0 DDRA1 DDRA0 Freescale Semiconductor ...
Page 99
... This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is selected. This bit has no effect for the XTAL or external oscillator options OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4 OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions Freescale Semiconductor DDRAx RESET PTAx Figure 12-3 ...
Page 100
... DDRA5–DDRA0 PTB6 PTB5 PTB4 PTB3 Unaffected by reset Figure 12-5. Port B Data Register (PTB) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Accesses to PTA Read Write Pin PTA5–PTA0 Pin PTA5–PTA0 PTA5–PTA0 PTA5–PTA0 2 1 Bit 0 PTB2 PTB1 PTB0 Freescale Semiconductor (3) (3) (5) ...
Page 101
... Table 12-2 DDRB PTB I/O Pin Bit Bit Mode ( Input, Hi Output don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect the input. Freescale Semiconductor DDRB6 DDRB5 DDRB4 DDRB3 NOTE DDRBx RESET PTBx Figure 12-7. Port B I/O Circuit summarizes the operation of the port B pins ...
Page 102
... I/O Pin Mode Read/Write (2) Input, V DDRB7–DDRB0 DD (4) DDRB7–DDRB0 Input, Hi-Z Output DDRB7–DDRB0 MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 PTBPUE2 PTBPUE2 PTBPUE0 Accesses to PTB Read Write Pin PTB7–PTB0 Pin PTB7–PTB0 PTB7–PTB0 PTB7–PTB0 Freescale Semiconductor (3) (3) ...
Page 103
... Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor Figure Chapter 5 Configuration Register Table 13-1. Signal Name Conventions Description MC68HLC908QY/QT Family Data Sheet, Rev. 3 13-1. The SIM is a system state controller (CONFIG) ...
Page 104
... BUSCLKX2 (FROM OSCILLATOR) INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) FORCED MON MODE ENTRY (FROM MENRST MODULE) INTERRUPT SOURCES CPU INTERFACE Figure 13-2. BUS CLOCK GENERATORS Freescale Semiconductor ...
Page 105
... RL if the RSTEN bit is set in the CONFIG2 register. BUSCLKX2 RST ADDRESS BUS PC Freescale Semiconductor 13.7.2 Stop Mode. 13.5 SIM Counter), but an external reset does not. Each of shows the relative timing. The RST pin function is only available Figure 13-3. External Reset Timing MC68HLC908QY/QT Family Data Sheet, Rev ...
Page 106
... Figure 13-4. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET POR LVI Figure 13-5. Sources of Internal Reset Table 13-2. Reset Recovery Timing Actual Number of Cycles 4163 (4096 + MC68HLC908QY/QT Family Data Sheet, Rev. 3 Figure 13-4. VECTOR HIGH 67 ( Freescale Semiconductor ...
Page 107
... BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time out. The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). Freescale Semiconductor 32 32 CYCLES ...
Page 108
... SSREC cleared in the configuration register 1 (CONFIG1). 108 Figure 2-1. Memory Map voltage falls to the LVI trip voltage V DD rises above V DD MC68HLC908QY/QT Family Data Sheet, Rev. 3 for memory ranges. . The LVI TRIPF . Sixty-four BUSCLKX4 TRIPR Freescale Semiconductor ...
Page 109
... If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. Freescale Semiconductor 13.7.2 Stop Mode 13.4.2 Active Resets from Internal Sources shows interrupt recovery timing. ...
Page 110
... I BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 13-7. Interrupt Processing MC68HLC908QY/QT Family Data Sheet, Rev. 3 STACK CPU REGISTERS SET I BIT UNSTACK CPU REGISTERS EXECUTE INSTRUCTION Freescale Semiconductor ...
Page 111
... I BIT ADDRESS BUS DUMMY SP DATA BUS DUMMY R/W MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS R/W INT1 INT2 Figure 13-10 Freescale Semiconductor SP – – – – – 1[7:0] PC – 1[15: Figure 13-8 Interrupt Entry SP – – – 1 CCR – 1[7:0] PC – 1[15:8] OPCODE Figure 13-9 ...
Page 112
... Address Flag — — $FFFE–$FFFF — — $FFFC–$FFFD IF1 $FFFA–$FFFB IF3 $FFF6–$FFF7 IF4 $FFF4–$FFF5 IF5 $FFF2–$FFF3 IF14 $FFE0–$FFE1 IF15 $FFDE–$FFDF 2 1 Bit 0 IF1 Freescale Semiconductor ...
Page 113
... Bit 1–7 — Always read 0 13.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 13.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output. (See Chapter 15 Development Freescale Semiconductor ...
Page 114
... WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 13-14. Wait Mode Entry Timing MC68HLC908QY/QT Family Data Sheet, Rev. 3 Figure 13-14 shows SAME SAME SAME Freescale Semiconductor ...
Page 115
... This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time by clearing the SSREC bit. Freescale Semiconductor show the timing for wait recovery. $6E0B $6E0C ...
Page 116
... Table 13-4 shows the mapping of these registers. Table 13-4. SIM Registers Register BSR SRSR BFCR MC68HLC908QY/QT Family Data Sheet, Rev. 3 shows stop mode entry timing and SAME SAME SAME SAME SP SP – – 2 Access Mode User User User Freescale Semiconductor SP – 3 ...
Page 117
... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ ≠ V TST 0 = POR or read of SRSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR Freescale Semiconductor PIN COP ...
Page 118
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break 118 MC68HLC908QY/QT Family Data Sheet, Rev Bit Freescale Semiconductor ...
Page 119
... The TIM shares two input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are listed in Table 14-1. The generic pin name appear in the text that follows. TIM Generic Pin Names: Full TIM Pin Names: Freescale Semiconductor Table 14-1. Pin Name Conventions TCH0 TCH1 PTA0/TCH0 PTA1/TCH1 MC68HLC908QY/QT Family Data Sheet, Rev ...
Page 120
... BYTES MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: 1536 BYTES USER FLASH MC68HLC908QY/QT Family Data Sheet, Rev. 3 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM Freescale Semiconductor ...
Page 121
... BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH Freescale Semiconductor PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A CH1F MS1A Figure 14-2. TIM Block Diagram MC68HLC908QY/QT Family Data Sheet, Rev ...
Page 122
... The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers ( that 122 MC68HLC908QY/QT Family Data Sheet, Rev. 3 14.4.3 Freescale Semiconductor ...
Page 123
... PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. OVERFLOW POLARITY = 1 TCHx (ELSxA = 0) POLARITY = 0 TCHx (ELSxA = 1) Figure 14-3. PWM Period and Pulse Width Freescale Semiconductor NOTE 14.9.1 TIM Status and Control OVERFLOW PERIOD PULSE WIDTH OUTPUT COMPARE MC68HLC908QY/QT Family Data Sheet, Rev. 3 Functional Description Register ...
Page 124
... User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 124 NOTE NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 14.4.4 Pulse Width Freescale Semiconductor ...
Page 125
... Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE =1. CHxF and CHxIE are in the TIM channel x status and control register. Freescale Semiconductor NOTE Registers. MC68HLC908QY/QT Family Data Sheet, Rev. 3 ...
Page 126
... TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0 and TSC1) • TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L) 126 13.8.2 Break Flag Control Register. Register.) When the PTA2/TCLK pin is the TIM clock input, MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 127
... TSTOP bit is cleared. When using TSTOP to stop the timer counter, see if any timer flags are set timer flag is set, it must be cleared by clearing TSTOP, then clearing the flag, then setting TSTOP again. Freescale Semiconductor ...
Page 128
... TIM Clock Source 0 0 Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ PTA2/TCLK NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 129
... Address: $0023 TMODH Bit 7 Read: Bit 15 Write: Reset: 1 Address: $0024 TMODL Bit 7 Read: Bit 7 Write: Reset: 1 Figure 14-6. TIM Counter Modulo Registers (TMODH:TMODL) Reset the TIM counter before writing to the TIM counter modulo registers. Freescale Semiconductor Bit 14 Bit 13 Bit 12 Bit Bit 6 ...
Page 130
... This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. 130 CH0IE MS0B MS0A ELS0B CH1IE MS1A ELS1B Registers (TSC0:TSC1) MC68HLC908QY/QT Family Data Sheet, Rev Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Freescale Semiconductor ...
Page 131
... ELSxB and ELSxA — Edge/Level Select Bits When channel input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. Freescale Semiconductor NOTE ELSxA Mode 0 Pin under port control ...
Page 132
... ELSxB and ELSxA work. Reset clears NOTE NOTE shows, the CHxMAX bit takes effect in the cycle after it is set OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Figure 14-8. CHxMAX Latency MC68HLC908QY/QT Family Data Sheet, Rev. 3 OVERFLOW OVERFLOW OUTPUT COMPARE Freescale Semiconductor ...
Page 133
... Bit 7 Write: Reset: Address: $0029 TCH1H Bit 7 Read: Bit 15 Write: Reset: Address: $02A TCH1L Bit 7 Read: Bit 7 Write: Reset: Figure 14-9. TIM Channel Registers (TCH0H/L:TCH1H/L) Freescale Semiconductor Bit 14 Bit 13 Bit 12 Bit 11 Indeterminate after reset Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset ...
Page 134
... Timer Interface Module (TIM) 134 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 135
... When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 15-2 shows the structure of the break module. Freescale Semiconductor MC68HLC908QY/QT Family Data Sheet, Rev. 3 135 ...
Page 136
... COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] MC68HLC908QY/QT Family Data Sheet, Rev. 3 CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM CONTROL BKPT (TO SIM) Freescale Semiconductor ...
Page 137
... Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) Freescale Semiconductor CAUTION 13.8.2 Break Flag Control Register MC68HLC908QY/QT Family Data Sheet, Rev. 3 Break Module (BRK) and the Break Interrupts subsection 137 ...
Page 138
... Figure 15-4. Break Address Register High (BRKH) Address: $FE0A Bit 7 Read: Bit 7 Write: Reset: 0 Figure 15-5. Break Address Register Low (BRKL) 138 BRKA Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit MC68HLC908QY/QT Family Data Sheet, Rev Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 139
... Wait mode was not exited by break interrupt 15.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU break state. Address: $FE03 Bit 7 Read: BCFE Write: Reset Figure 15-8. Break Flag Control Register (BFCR) Freescale Semiconductor ...
Page 140
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 140 ( reset vector is blank ($FFFE and $FFFF contain TST MC68HLC908QY/QT Family Data Sheet, Rev TST Figure 15-10, Figure 15-11, Freescale Semiconductor ...
Page 141
... PTA0 = 1, FROM Table 15-1 RESET VECTOR BLANK? YES FORCED MONITOR MODE DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) Figure 15-9. Simplified Monitor Mode Entry Flowchart Freescale Semiconductor POR RESET YES NO IRQ = V ? TST NO NORMAL USER MODE HOST SENDS 8 SECURITY BYTES YES IS RESET POR? ...
Page 142
... MC68HLC908QY/QT Family Data Sheet, Rev RST (PTA3) OSC1 (PTA5) PTA1 IRQ (PTA2) PTA4 PTA0 Value not critical N.C. RST (PTA3 OSC1 (PTA5) PTA1 * IRQ (PTA2) PTA4 PTA0 Value not critical Freescale Semiconductor V DD 0.1 µ kΩ kΩ 0.1 µF N.C. N.C. ...
Page 143
... If $FFFE and $FFFF contain $FF (erased state): – IRQ = V (internal oscillator is selected, no external clock required) SS The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the values on PTA1 and PTA4 pins can be changed. Freescale Semiconductor µF 1 µ kΩ ...
Page 144
... OSC1. 9.8304 2.4576 Provide external 9600 MHz MHz clock at OSC1. 1.0 MHz Internal clock is X 4800 (Trimmed) active OSC1 — — [13] 15.3.2 Security). After the TST ) then the chip will still be operating in lowered, the BIH and TST is applied to TST Freescale Semiconductor is ...
Page 145
... Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors. Modes Reset Vector High User $FFFE Monitor $FEFE Freescale Semiconductor NOTE , the MCU will come out of reset in user mode. Internal TST Figure 15-12. NOTE Table 15-2. Mode Difference Functions ...
Page 146
... Wait one bit time after each echo before sending the next byte. 146 BIT 6 BIT 2 BIT 3 BIT 4 BIT 5 Figure 15-13. Monitor Data Format MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO Figure 15-14. Break Transaction Table 15-1. NOTE MC68HLC908QY/QT Family Data Sheet, Rev. 3 NEXT START STOP BIT 7 BIT BIT Freescale Semiconductor ...
Page 147
... Table 15-3. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A SENT TO MONITOR READ READ ECHO Freescale Semiconductor ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte ...
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... Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH LOW HIGH LOW Command Sequence FROM HOST IREAD IREAD DATA Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO MC68HLC908QY/QT Family Data Sheet, Rev. 3 DATA DATA DATA RETURN Freescale Semiconductor ...
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... CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value The high and low bytes of the program counter are at addresses and Figure 15-17. Stack Pointer at Monitor Mode Entry Freescale Semiconductor Command Sequence SP READSP ...
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... Data return delay, approximately 2 bit times 3 = Wait 1 bit time before sending next byte 4 = Wait until clock is stable and monitor runs Figure 15-18. Monitor Mode Entry Timing 150 NOTE Figure 15-18. NOTE 4096 + 32 CGMXCLK CYCLES FROM HOST FROM MCU MC68HLC908QY/QT Family Data Sheet, Rev Freescale Semiconductor ...
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... For proper operation recommended that V ≤ (V range unused inputs are connected to an appropriate logic voltage level (for example, either V Freescale Semiconductor NOTE for guaranteed operating (1) Symbol , and PTA0— ...
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... MC68HLC908QY/QT Family Data Sheet, Rev. 3 Symbol Value Unit T – ° 2 2.2 to 3.6 Value 105 142 θ 173 133 P User determined I K/(T + 273°C) I 273° θ θ 150 JM With this value Freescale Semiconductor Temp Code C — C — Unit °C W/°C °C °C and ...
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... Digital I/O ports Hi-Z leakage current Typical at 25°C Digital input only ports leakage current (PA2/IRQ/KBI2) Capacitance Ports (as input) Ports (as output) (3) POR rearm voltage (4) POR rise time ramp rate Monitor mode entry voltage (5) Pullup resistors PTA0–PTA5, PTB0–PTB7 Freescale Semiconductor Symbol V OH < DDMAX < DDMAX ...
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... Symbol Min Max — Bus t 500 — cyc t 400 — 400 — ILIH t (2) — Note ILIL unless otherwise noted cyc Freescale Semiconductor Unit Unit MHz cyc ...
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... Figure 16-2. Typical 3-Volt Output High Voltage 1.5 1.0 0.5 0.0 0 Figure 16-3. Typical 3-Volt Output Low Voltage Freescale Semiconductor -5 -10 -15 IOH (mA) versus Output High Current (25° IOL (mA) versus Output Low Current (25°C) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Typical 3 ...
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... MC68HLC908QY/QT Family Data Sheet, Rev. 3 Min Typ Max — 4.0 — 30 32.768 100 2 — — 8 — 12.5 — — — — — 100 330 470 See Figure 16-4 MCU 3V OSC1 2. EXT (25°C) EXT Freescale Semiconductor Unit MHz kHz MHz MHz pF — — MΩ kΩ — ...
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... V or less from rail loads. On the 8-pin versions, port B is configured as DD inputs with pullups enabled. 2.5 2 1 Figure 16-5. Typical Run Current versus MHz for Internal Oscillator, f Bus Freescale Semiconductor Bus Freq. Voltage (MHz) 3.0 1 2.2 1 3.0 1 2.2 1 3.0 2.2 2 ...
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... Figure 16-7. Typical Stop Current versus V 158 2 (V) DD INT OSC w/ ADC INT OSC w/o ADC 32K CRYSTAL w/ ADC 32K CRYSTAL w/o ADC = 8 kHz for Crystal Oscillator) Bus 2.4 2.6 2 (V) DD MC68HLC908QY/QT Family Data Sheet, Rev. 3 3.5 4 (25°C) DD 3.2 3.4 3.6 3.8 (25°C) DD Freescale Semiconductor ...
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... Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current. Freescale Semiconductor Analog-to-Digital (ADC) Converter Characteristics Characteristic Symbol ...
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... FALLING EDGE INPUT CAPTURE BOTH EDGES TCLK 160 t TLTL TLTL t TLTL TCH t TCL Figure 16-8. Timer Input Timing MC68HLC908QY/QT Family Data Sheet, Rev. 3 Symbol Min Max — TH (1) — Note TLTL — TCL TCH cyc . cyc Freescale Semiconductor Unit t cyc t cyc ns ...
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... Endurance, please refer to Engineering Bulletin EB619. 5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618. Freescale Semiconductor Symbol V RDR — ...
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... Electrical Specifications 162 MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... P = Plastic dual in-line package (PDIP Small outline integrated circuit package (SOIC Thin shrink small outline package (TSSOP Dual flat no lead (DFN) 17.3 Package Dimensions Refer to the following pages for detailed package dimensions. Freescale Semiconductor Table 17-1. MC Order Numbers ADC FLASH Memory — 1536 bytes ...
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... All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components ...