MC908AZ60AMFUE Freescale Semiconductor, MC908AZ60AMFUE Datasheet - Page 124

IC MCU FLASH 8.4MHZ 60K 64QFP

MC908AZ60AMFUE

Manufacturer Part Number
MC908AZ60AMFUE
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ60AMFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-QFP
Processor Series
HC08AZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8.4 MHz
Number Of Programmable I/os
52
Number Of Timers
8
Operating Supply Voltage
5 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 15 Channel
Package
64PQFP
Family Name
HC08
Maximum Speed
8.4 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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System Integration Module (SIM)
9.7 SIM Registers
The SIM has three memory mapped registers.
9.7.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break caused an exit from wait mode.
BW — SIM Break Wait
9.7.2 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading it. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bits can both be set if the power supply has a slow rise time.
POR — Power-On Reset Bit
PIN — External Reset Bit
COP — Computer Operating Properly Reset Bit
124
This status bit is useful in applications requiring a return to wait mode after exiting from a break
interrupt. Clear BW by writing a 0 to it. Reset clears BW.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
1 = Last reset caused by POR circuit
0 = Read of SRSR
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
1 = Last reset caused by COP counter
0 = POR or read of SRSR
Address:
Address:
Reset:
Read:
Read:
Write:
Write:
POR:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$FE00
$FE01
POR
Bit 7
Bit 7
R
R
1
Figure 9-17. SIM Break Status Register (SBSR)
Figure 9-18. SIM Reset Status Register (SRSR)
= Reserved
= Unimplemented
PIN
R
6
6
0
COP
R
5
5
0
ILOP
R
4
4
0
NOTE: Writing a logic 0 clears BW
ILAD
R
3
3
0
R
2
2
0
0
See Note
BW
LVI
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 0
R
0
0

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