MCIMX512CJM6C Freescale Semiconductor, MCIMX512CJM6C Datasheet - Page 116

• Manufacturer Part Number: MCIMX512CJM6C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX512CJM6C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
Table 91
116
1
Values provided where applicable.
tcable1
tcable2
tskew1
tskew2
tskew3
tskew4
tskew5
tskew6
Name
ti_dh
ti_ds
tbuf
tsui
tco
tsu
thi
T
shows ATA timing parameters.
Bus clock period (ipg_clk_ata)
Set-up time ata_data to ata_iordy edge (UDMA-in only)
Hold time ata_iordy edge to ata_data (UDMA-in only)
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
Set-up time ata_data to bus clock L-to-H
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
Max difference in buffer propagation delay for any of following signals ata_iordy,
ata_data (read)
Max buffer propagation delay
Cable propagation delay for ata_data
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,
ata_dmack
Max difference in cable propagation delay between ata_iordy and ata_data (read)
Max difference in cable propagation delay between (ata_dior, ata_diow,
ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Max difference in cable propagation delay without accounting for ground bounce
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Table 91. P-ATA Timing Parameters
Description
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA2, UDMA3
UDMA0
UDMA1
UDMA4
Peripheral clock frequency
Contributing Factor
Freescale Semiconductor
Transceiver
Transceiver
Transceiver
12.0 ns
Value/
8.5 ns
8.5 ns
2.5 ns
5.0 ns
Cable
Cable
Cable
Cable
Cable
15 ns
10 ns
7 ns
5 ns
7 ns
1