PIC16F688-E/ML Microchip Technology, PIC16F688-E/ML Datasheet - Page 101

• Manufacturer Part Number: PIC16F688-E/ML
• Description: IC PIC MCU FLASH 4KX14 16QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, RS- 232, SCI, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Details

6.2.6
1997 Microchip Technology Inc.
Program Memory Paging
Some devices have program memory sizes greater then 2K words, but the CALL and GOTO
instructions only have a 11-bit address range. This 11-bit address range allows a branch within
a 2K program memory page size. To allow CALL and GOTO instructions to address the entire 1K
program memory address range, there must be another two bits to specify the program memory
page. These paging bits come from the PCLATH<4:3> bits
GOTO instruction, the user must ensure that page bits (PCLATH<4:3>) are programmed so that
the desired program memory page is addressed
tions is executed, the entire 13-bit PC is POPed from the stack. Therefore, manipulation of the
PCLATH<4:3> is not required for the return instructions.
Example 6-1
assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are
used).
Example 6-1: Call of a Subroutine in Page1 from Page0
SUB1_P1:
Note:
ORG 0x500
BSF
CALL
ORG 0x900
RETURN
:
:
:
Section 6. Memory Organization
Devices with program memory sizes 2K words and less, ignore both paging bits
(PCLATH<4:3>), which are used to access program memory when more than one
page is available. The use of PCLATH<4:3> as general purpose read/write bits (for
these devices) is not recommended since this may affect upward compatibility with
future products.
Devices with program memory sizes between 2K words and 4K words, ignore the
paging bit (PCLATH<4>), which is used to access program memory pages 2 and 3
(1000h - 1FFFh). The use of PCLATH<4> as a general purpose read/write bit (for
these devices) is not recommended since this may affect upward compatibility with
future products.
shows the calling of a subroutine in page 1 of the program memory. This example
PCLATH,3
SUB1_P1
; Select Page1 (800h-FFFh)
; Call subroutine in Page1 (800h-FFFh)
;
;
;
; called subroutine Page1 (800h-FFFh)
;
; return to Call subroutine in Page0 (000h-7FFh)
;
(Figure
6-2). When one of the return instruc-
(Figure
6-2). When doing a CALL or
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