PIC16F688-E/ML Microchip Technology, PIC16F688-E/ML Datasheet - Page 165

• Manufacturer Part Number: PIC16F688-E/ML
• Description: IC PIC MCU FLASH 4KX14 16QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, RS- 232, SCI, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Details

10.4
10.5
10.6
PORTD<7:0>
PORTD<7:0>
1997 Microchip Technology Inc.
PSPIF
PSPIF
OBF
OBF
CS
WR
RD
IBF
CS
WR
RD
IBF
Note:
Operation in Sleep Mode
Effect of a Reset
PSP Waveforms
The IBF flag bit is inhibited from being cleared until after this point.
Q1
Q1
When in sleep mode the microprocessor may still read and write the Parallel Slave Port. These
actions will set the PSPIF bit. If the PSP interrupts are enabled, this will wake the processor from
sleep mode so that the PSP data latch may be either read, or written with the next value for the
microprocessor.
After any reset the PSP is disabled and PORTD and PORTE are forced to their default mode.
Figure 10-2
Figure 10-3
Figure 10-2: Parallel Slave Port Write Waveforms
Figure 10-3: Parallel Slave Port Read Waveforms
Q2
Q2
shows the waveform for a read of the PSP by the microprocessor.
shows the waveform for a write from the microprocessor to the PSP, while
Q3
Q3
Section 10. Parallel Slave Port
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
DS31010A-page 10-5
Q4
Q4
10