PIC16F688-E/ML Microchip Technology, PIC16F688-E/ML Datasheet - Page 595

• Manufacturer Part Number: PIC16F688-E/ML
• Description: IC PIC MCU FLASH 4KX14 16QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, RS- 232, SCI, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Details

Figure 30-11: Example SPI Slave Mode Timing (CKE = 0)
Table 30-23:
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
Param.
1997 Microchip Technology Inc.
No.
71A
72A
73A
70
71
72
73
74
75
76
77
78
79
80
83
SCK
(CKP = 0)
(CKP = 1)
SDO
SDI
SDI
SS
SCK
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Refer to
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
T
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ
TscR
TscF
TscH2doV,
TscL2doV
TscH2ssH,
TscL2ssH
B
Symbol
2
B
Example SPI Mode Requirements (Slave Mode Timing (CKE = 0)
Figure 30-1
Characteristic
SS to SCK or SCK input
SCK input high time
(slave mode)
SCK input low time
(slave mode)
Setup time of SDI data input to SCK edge
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise time PIC16CXXX
SDO data output fall time
SS to SDO output hi-impedance
SCK output rise time
(master mode)
SCK output fall time (master mode)
SDO data output valid
after SCK edge
SS
Section 30. Electrical Specifications
70
for load conditions.
after SCK edge
80
71
73
MSb IN
MSb
74
72
75, 76
Continuous
Single Byte
Continuous
Single Byte
PIC16LCXXX
PIC16CXXX
PIC16LCXXX
PIC16CXXX
PIC16LCXXX
BIT6 - - - - - -1
BIT6 - - - -1
1.25T
1.25T
1.5T
1.5T
78
79
Min
T
100
100
CY
CY
40
40
10
—
—
—
—
—
CY
CY
CY
+ 40
+ 40
+ 30
+ 30
LSb
79
78
LSb IN
Typ† Max Units
10
20
10
10
20
10
83
—
—
—
—
—
—
—
—
—
—
—
—
100
77
25
45
25
50
25
45
25
50
—
—
—
—
—
—
—
—
—
DS31030A-page 30-25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Conditions
30