AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 177

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.23.10
13.23.11
7734P–AVR–08/10
PSCR Input Capture Register – PICR0H and PICR0L
PSCR Interrupt Mask Register – PIM0
Table 13-14.
• Bit 7 – PCST0 : PSCR Capture Software Trig bit
Set this bit to trigger off a capture of the PSCR counter. When reading, if this bit is set it means that the
capture operation was triggered by PCST0 setting otherwise it means that the capture operation was trig-
gered by a PSCR input.
The Input Capture is updated with the PSCR counter value each time an event occurs on the enabled
PSCR input pin (or optionally on the Analog Comparator output) if the capture function is enabled (bit
PCAE0x in PFRC0x register is set).
The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read simultane-
ously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte
register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers.
Bit
Read/Write
Initial Value
• Bit 7- 5 – Reserved
• Bit 4 – PEVE0B : PSCR External Event B Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block B gener-
ates also an interrupt.
• Bit 3 – PEVE0A : PSCR External Event A Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block A gener-
ates also an interrupt.
Bit
Read/Write
Initial Value
PRFM0x3:0
1010b
1011b
1100b
1101b
1110b
1111b
7
-
R
0
7
PCST0
R
0
Level Sensitivity and Fault Mode Operation
Description
Reserved (do not use)
PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate
Output
Reserved (do not use)
6
-
R
0
6
–
R
0
5
-
R
0
5
–
R
0
4
PEVE0B
R/W
0
0
4
–
R
PICR0[7:0]
3
PEVE0A
R/W
0
3
PICR0[11:8]
R
0
2
-
R
0
2
R
0
1
0
PEOEPE0 PEOPE0
R
1
R
0
AT90PWM81
0
R/W
0
0
R
0
PIM0
PICR0H
PICR0L
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