AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 241

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.7.1
20.7.2
20.7.3
20.7.4
20.7.5
20.7.6
7734P–AVR–08/10
Performing Page Erase by SPM
Filling the Temporary Buffer (Page Loading)
Performing a Page Write
Using the SPM Interrupt
Consideration While Updating BLS
Prevent Reading the RWW Section During Self-Programming
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute
SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address
must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this
operation.
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in
the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase
after a Page Write operation or by writing the RWWSRE bit in SPMCSR. It is also erased after a system
reset. Note that it is not possible to write more than one time to each address without erasing the tempo-
rary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute
SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address
must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit
in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register
in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to
avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the
interrupts is described in Section “Moving Interrupts Between Application and Boot Space”, page 64.
Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock
bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader,
and further software updates might be impossible. If it is not necessary to change the Boot Loader soft-
ware itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from
any internal software changes.
During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for
reading. The user software itself must prevent that this section is addressed during the self programming
operation. The RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-Pro-
gramming the Interrupt Vector table should be moved to the BLS as described in Section “Moving
Interrupts Between Application and Boot Space”, page 64, or the interrupts must be disabled. Before
addressing the RWW section after the programming is completed, the user software must clear the
RWWSB by writing the RWWSRE. See
244
• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
• Page Erase to the NRWW section: The CPU is halted during the operation.
• Page Write to the RWW section: The NRWW section can be read during the Page Write.
• Page Write to the NRWW section: The CPU is halted during the operation.
for an example.
“Simple Assembly Code Example for a Boot Loader” on page
AT90PWM81
241