AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 243

• Manufacturer Part Number: AT90PWM81-16SN
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.7.10
7734P–AVR–08/10
Reading the Signature Row from Software
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is exe-
cuted within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the
Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to
on page 249
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed,
will be read as one.
To read the Signature Row from software, load the Z-pointer with the signature byte address given in
Table 20-5
three CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the signature byte value will be
loaded in the destination register. The SIGRD and SPMEN bits will auto-clear upon completion of read-
ing the Signature Row Lock bits or if no LPM instruction is executed within three CPU cycles. When
SIGRD and SPMEN are cleared, LPM will work as described in the ”AVR Instruction Set” description.
Table 20-5.
Bit
Rd
Device ID 0, Manufacturer ID
OSCAL 8M, RC-OSC calibration
Device ID 1, Flash size
Reserved
Device ID 2, Device
Temperature Sensor Offset : TSOFFSET
Reserved
Temperature Sensor Gain : TSGAIN
Lot number at sort, byte 2, ASCII
Lot number at sort, Byte 1, ASCII (most left
lot#)
Lot number at sort, byte 2, ASCII
Lot number at sort, Byte 1, ASCII
Lot number at sort, byte 2, ASCII
Lot number at sort, Byte 1, ASCII
Final test Amb VRef : LOW BYTE
Final Test Amb VRef : HIGH BYTE
Final Test Hot VRef : LOW BYTE ( only a
Read)
Final Test Hot VRef : HIGH BYTE( only a
Read)
1.TSGAIN typical value is 0x80=128
(4)
(5)
and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction is executed within
for detailed description and mapping of the Extended Fuse byte.
Signature Byte
Signature Row Addressing
7
–
6
–
(2)
(3)
(1)
5
–
Address
4
–
0x3D
0x0E
0x3C
0x3E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x0F
0x10
0x11
0x12
0x13
0x3F
3
EFB3
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
Data
1EH
93H
88H
2
EFB2
1
EFB1
AT90PWM81
0
EFB0
Table 21-4
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