DSPIC33FJ12MC202-I/ML Microchip Technology, DSPIC33FJ12MC202-I/ML Datasheet
DSPIC33FJ12MC202-I/ML
Specifications of DSPIC33FJ12MC202-I/ML
Related parts for DSPIC33FJ12MC202-I/ML
DSPIC33FJ12MC202-I/ML Summary of contents
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... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70265D ...
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... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... FIFO on each capture • Output Compare (up to two channels): - Single or Dual 16-bit Compare mode - 16-bit Glitchless PWM mode © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Interrupt Controller: • 5-cycle latency • available interrupt sources • three external interrupts • ...
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... LIN bus support ® - IrDA encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS Packaging: • 20-pin SDIP/SOIC/SSOP • 28-pin SDIP/SOIC/SSOP/QFN Note: See Table 1 for the exact peripheral features per device. Preliminary © 2009 Microchip Technology Inc. ...
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... Table 1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ12MC201/202 CONTROLLER FAMILIES Device Pins dsPIC33FJ12MC201 dsPIC33FJ12MC202 Note 1: Only two out of three timers are remappable. 2: Only PWM fault inputs are remappable. 3: Only two out of three interrupts are remappable. © 2009 Microchip Technology Inc. ...
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... TMS/PWM1L3/RP11 V TDI/PWM1H3/RP10 CAP DDCORE (1) /CN1/RB4 11 18 TDO/PWM2L1/SDA1/RP9 TCK/PWM2H1/SCL1/RP8 INT0/RP7 (1) ASCL1/RP6 /CN27/RB5 14 15 Preliminary = Pins are tolerant (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN21/RB9 (1) /CN22/RB8 /CN23/RB7 = Pins are tolerant (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 (1) /CN24/RB6 © 2009 Microchip Technology Inc. ...
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... Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 PWM1L2/RP13 21 2 PWM1H2/RP12 TMS/PWM1L3/RP11 dsPIC33FJ12MC202 4 18 TDI/PWM1H3/RP10 CAP TDO/PWM2L1/SDA1/RP9 Preliminary = Pins are tolerant ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70265D-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ12MC201/ 202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265D-page 7 ...
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... Latch Control Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR OC/ UART1 ADC1 PWM1-2 QEI CNx I2C1 Preliminary PORTA PORTB 16 Remappable Pins PWM 2 Ch PWM 6 Ch © 2009 Microchip Technology Inc. ...
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... Yes Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Description External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. Analog = Analog input O = Output Preliminary P = Power I = Input © 2009 Microchip Technology Inc. ...
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... REF reference for ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
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... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2- EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F JP C and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...
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... REAL ICE™ In-Circuit Debugger User's Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “ ...
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... DS70265D-page 14 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternately, connect 10k resistor to V unused pins and drive the output to logic low. Preliminary © 2009 Microchip Technology Inc ...
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... MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts ...
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... Data Latch Data Latch PCL X RAM Y RAM Address Address Loop Control Latch Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2009 Microchip Technology Inc. ...
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... AD39 DSP ACCA Accumulators ACCB PC22 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 ...
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... The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70265D-page 18 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (2) Preliminary ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70265D-page 20 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...
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... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265D-page 21 ...
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... A block diagram of the DSP engine is shown in Figure 3-3. TABLE 3-1: DSP INSTRUCTIONS SUMMARY Algebraic Instruction Operation CLR – – y) EDAC MAC MAC No change in A MOVSAC MPY MPY A = – MPY – MSC Preliminary © 2009 Microchip Technology Inc. ACC Write Back Yes Yes 2 No Yes Yes ...
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... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill DS70265D-page 23 ...
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... Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section 7.0 “Interrupt Controller”). This allows the user application to take immediate action; for example, to correct system gain. Preliminary previously and the SAT<A:B> © 2009 Microchip Technology Inc. ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 3.6.3 ACCUMULATOR ‘WRITE BACK’ The MAC class of instructions (with the exception of MPY, MPY ...
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... DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. Preliminary © 2009 Microchip Technology Inc. ...
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... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33FJ12MC201/202 DEVICES © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 4.1 Program Address Space The program dsPIC33FJ12MC201/202 devices is 4M instructions ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. least significant word (lsw Instruction Width Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2009 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS70265D-page 30 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0x0BFE 0x0C00 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2009 Microchip Technology Inc. ...
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... X and Y address space also the X data prefetch path for the dual operand DSP instructions (MAC class). © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC202 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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... TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ12MC202 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA — — — ...
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TABLE 4-10: 2-OUTPUT PWM2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P2TCON 05C0 PTEN — PTSIDL — P2TMR 05C2 PTDIR P2TPER 05C4 — P2SECMP 05C6 SEVTDIR PWM2CON1 05C8 — — — — PWM2CON2 05CA ...
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TABLE 4-13: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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... TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ12MC202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
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TABLE 4-16: ADC1 REGISTER MAP FOR dsPIC33FJ12MC201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... RPINR21 06AA — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12MC202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — ...
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... ODCA 02C6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-21: PORTB REGISTER MAP FOR dsPIC33FJ12MC202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C8 TRISB15 TRISB14 ...
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TABLE 4-23: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
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... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. Preliminary © 2009 Microchip Technology Inc. addressing modes are ...
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... Not all instructions support all the address- ing modes given above. Individual instruc- tions may support different subsets of these addressing modes. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Description The address of the file register is specified explicitly. The contents of a register are accessed directly. ...
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... MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary the difference between the © 2009 Microchip Technology Inc. ...
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... The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 4.5.1 BIT-REVERSED ADDRESSING ...
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... TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70265D-page 48 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word, Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal © 2009 Microchip Technology Inc. ...
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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
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... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70265D-page 50 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2009 Microchip Technology Inc. ...
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... FIGURE 4-8: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 • TBLRDH (Table Read High Word mode, this instruction maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2009 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ instructions (192 bytes sin- gle program memory word, and erase program mem- source ...
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... NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. Preliminary PROGRAMMING TIME T )% × FRC Accuracy FRC Tuning 11064 Cycles = × × 0.05 1 0.00375 – 11064 Cycles = × × 0.05 – 1 0.00375 – © 2009 Microchip Technology Inc. ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) U-0 U-0 — — ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70265D-page 56 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
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... W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2009 Microchip Technology Inc. ...
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... DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Any active source of Reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state, and some are unaffected. ...
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... SWDTEN bit setting. DS70265D-page 60 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) (CONTINUED) ...
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... Preliminary ) after a PWRT ensures that the system PWRT for more FSCM Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2009 Microchip Technology Inc. ...
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... BOR BOR extension time 100 μs maximum T BOR T Programmable 0-128 ms nominal PWRT power-up time delay 900 μs maximum T Fail-safe Clock FSCM Monitor Delay © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Vbor V BOR T BOR 3 T PWRT T OSCD Reset Time has elapsed. ...
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... V ) for proper DD DD BOR crosses the V threshold and the DD BOR ensures the BOR ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V BOR PWRT trip point. BOR V BOR V BOR V BOR © 2009 Microchip Technology Inc. DD ...
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... Watchdog Reset. Refer to “Watchdog Timer (WDT)” for more information on Watchdog Reset. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 6.7 Trap Conflict Reset If a lower-priority hard trap occurs while a higher-prior- ity trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive ...
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... MCLR Reset RESET instruction WDT Time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Preliminary Cleared by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR © 2009 Microchip Technology Inc. ...
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... These are summarized in Table 7-1 and Table 7-2. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1 ...
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... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70265D-page 68 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC33FJ12MC201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
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... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2009 Microchip Technology Inc. ...
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... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 7.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt ...
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... R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...
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... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 COVAERR COVBERR ...
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... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70265D-page 74 Preliminary © 2009 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — ...
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... Interrupt request has not occurred DS70265D-page 76 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265D-page 77 ...
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... Interrupt request has not occurred DS70265D-page 78 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — QEIIF ...
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... Unimplemented: Read as ‘0’ DS70265D-page 80 U-0 U-0 R/W-0 — — FLTA2IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 U-0 PWM2IF — bit 8 U-0 U-0 U1EIF — bit Bit is unknown ...
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... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70265D-page 82 Preliminary © 2009 Microchip Technology Inc. ...
Page 85
... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — ...
Page 86
... Unimplemented: Read as ‘0’ DS70265D-page 84 U-0 U-0 R/W-0 — — QEIIE U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 U-0 PWM1IE — bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 87
... Interrupt request not enabled bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — FLA2IE U-0 ...
Page 88
... Interrupt is priority 1 000 = Interrupt source is disabled DS70265D-page 86 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 89
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-1 — ...
Page 90
... Interrupt is priority 1 000 = Interrupt source is disabled DS70265D-page 88 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-1 — — — R/W-0 ...
Page 92
... Interrupt is priority 1 000 = Interrupt source is disabled DS70265D-page 90 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...
Page 94
... Unimplemented: Read as ‘0’ DS70265D-page 92 U-0 U-0 U-1 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...
Page 96
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 97
... PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — R/W-0 U-0 U-0 — ...
Page 98
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70265D-page 96 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 99
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 100
... NOTES: DS70265D-page 98 Preliminary © 2009 Microchip Technology Inc. ...
Page 101
... Note 1: See Figure 8-2 for PLL details the Oscillator is used with modes, an extended parallel resistor with the value of 1 MΩ must be connected. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 • An on-chip Phase-Locked Loop (PLL) to scale the internal operating frequency to the required system clock frequency • ...
Page 102
... MHz are supported by the dsPIC33FJ12MC201/202 architecture. Instruction execution speed or device operating frequency given by: CY EQUATION 8-1: DEVICE OPERATING FREQUENCY F CY Preliminary © 2009 Microchip Technology Inc. device operation. PLL bits, FNOSC<2:0> bits, POSCMD<1:0> is divided OSC ) and the ...
Page 103
... PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. • If PLLPRE<4:0> then This yields a VCO input of 10 MHz, which is within the acceptable range of 0 ...
Page 104
... This is the default oscillator mode for an unprogrammed (erased) device. DS70265D-page 102 Oscillator POSCMD<1:0> Source Internal xx Internal xx Internal xx Secondary xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx Preliminary © 2009 Microchip Technology Inc. FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 011 011 1 011 010 010 1 010 1 001 1 000 ...
Page 105
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) ...
Page 106
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70265D-page 104 (1) (CONTINUED) Preliminary © 2009 Microchip Technology Inc. ...
Page 107
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 ...
Page 108
... DS70265D-page 106 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 109
... Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — ...
Page 110
... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. Preliminary and the CF Section 7. “Oscillator” © 2009 Microchip Technology Inc. ...
Page 111
... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 9.2 Instruction-Based Power-Saving Modes dsPIC33FJ12MC201/202 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 112
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible ® DSC © 2009 Microchip Technology Inc. ...
Page 113
... ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 ...
Page 114
... DS70265D-page 112 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown ...
Page 115
... Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4 PWM2MD: PWM2 Module Disable bit 1 = PWM2 module is disabled 0 = PWM2 module is enabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-0 ...
Page 116
... NOTES: DS70265D-page 114 Preliminary © 2009 Microchip Technology Inc. ...
Page 117
... CK WR Port Data Latch Read LAT Read Port © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as source ...
Page 118
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary © 2009 Microchip Technology Inc. ...
Page 119
... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral ...
Page 120
... UPDN Output Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> FLTA1R<4:0> FLTA2R<4:0> QEA1R<4:0> QEB1R<4:0> INDX1R<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPnR<4:0> Output enable RPn Output Data 19 26 © 2009 Microchip Technology Inc. ...
Page 121
... IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 RPn tied to default port pin 00000 RPn tied to UART1 Transmit ...
Page 122
... Unimplemented: Read as ‘0’ DS70265D-page 120 R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 123
... INTR2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R< ...
Page 124
... Input tied to RP1 00000 = Input tied to RP0 DS70265D-page 122 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 125
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> ...
Page 126
... Input tied to RP1 00000 = Input tied to RP0 DS70265D-page 124 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 OCFAR< ...
Page 128
... Input tied to RP0 DS70265D-page 126 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 FLTA2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... QEA1R<4:0>: Assign A (QEA) to the corresponding pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 QEB1R<4:0> R/W-1 R/W-1 R/W-1 QEA1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 130
... Input tied to RP0 DS70265D-page 128 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INDX1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 131
... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> ...
Page 132
... Input tied to RP1 00000 = Input tied to RP0 DS70265D-page 130 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 133
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 SS1R< ...
Page 134
... Bit is cleared R/W-0 R/W-0 R/W-0 RP3R<4:0> R/W-0 R/W-0 R/W-0 RP2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 135
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 ...
Page 136
... Bit is cleared R/W-0 R/W-0 R/W-0 RP11R<4:0> R/W-0 R/W-0 R/W-0 RP10R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 137
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 ...
Page 138
... NOTES: DS70265D-page 136 Preliminary © 2009 Microchip Technology Inc. ...
Page 139
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the source ...
Page 140
... Unimplemented: Read as ‘0’ DS70265D-page 138 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 141
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an generated with the Timer3 interrupt flags. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 12.1 32-bit Operation To configure the Timer2/3 feature timers for 32-bit operation: 1. ...
Page 142
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70265D-page 140 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2009 Microchip Technology Inc. ...
Page 143
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70265D-page 141 ...
Page 144
... Unimplemented: Read as ‘0’ DS70265D-page 142 U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 145
... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T2CON<3>) register, these bits have no effect. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 (1) — ...
Page 146
... NOTES: DS70265D-page 144 Preliminary © 2009 Microchip Technology Inc. ...
Page 147
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 3. Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin ...
Page 148
... Input capture module turned off DS70265D-page 146 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 149
... OUTPUT COMPARE MODULE BLOCK DIAGRAM OCxRS OCxR Comparator OCTSEL TMR3 TMR2 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 The Output Compare module has multiple operating modes: • Active-Low One-Shot mode • Active-High One-Shot mode • Toggle mode source. To • Delayed One-Shot mode • Continuous Pulse mode • ...
Page 150
... OCx Rising edge 0 OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Preliminary — © 2009 Microchip Technology Inc. ...
Page 151
... TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle Mode (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse Mode (OCM = 101) PWM Mode (OCM = 110 or 111) © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Timer is reset on period match Preliminary DS70265D-page 149 ...
Page 152
... DS70265D-page 150 U-0 U-0 U-0 — — — R-0 HC R/W-0 R/W-0 OCFLT OCTSEL HS = Set in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 OCM<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... Fault pins to optionally drive each of the PWM output pins to a defined state • Duty cycle updates configurable to be immediate or synchronized to the PWM time base © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 15.1 PWM1: 6-Channel PWM Module This module simplifies the task of generating multiple synchronized PWM outputs ...
Page 154
... Override Logic PWM Channel 2 Dead-Time Generator 2 Generator and Override Logic PWM Channel 1 Dead-Time Generator 1 Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR Preliminary PWM1H3 PWM1L3 PWM1H2 Output PWM1L2 Driver PWM1H1 Block PWM1L1 FLTA1 Special Event Trigger © 2009 Microchip Technology Inc. ...
Page 155
... Fault Pin Control SFRs P2FLTACON PWM Manual P2OVDCON Control SFR P2TMR Comparator P2TPER P2TPER Buffer P2TCON Comparator P2SECMP PWM Time Base © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 PWM Generator 1 P2DC1Buffer P2DC1 Comparator Channel 1 Dead-Time Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR ...
Page 156
... R/W-0 R/W-0 R/W-0 PTCKPS<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1:64 prescale) CY (1:16 prescale) CY (1:4 prescale) CY (1:1 prescale) CY Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 PTMOD<1:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 157
... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ...
Page 158
... SEVTCMP<14:8> R/W-0 R/W-0 R/W-0 (2) SEVTCMP<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) TMR<15>) to generate the Special Event Trigger. X TMR<14:0> to generate the Special Event Trigger. X Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 159
... Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. 2: PWM2 supports only one PWM I/O pin pair. PWM1 on dsPIC33FJ12MC201 devices supports only two PWM I/O pin pairs. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (2) U-0 ...
Page 160
... Updates from Duty Cycle and Period Buffer registers are enabled DS70265D-page 158 U-0 R/W-0 R/W-0 — SEVOPS<3:0> U-0 U-0 R/W-0 — — IUE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared boundary CY Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 OSYNC UDIS bit Bit is unknown ...
Page 161
... Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 DTB<5:0> ...
Page 162
... DS70265D-page 160 (1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DTS3I DTS2A DTS2I U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 DTS1A DTS1I bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 163
... PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: PWM2 supports only one PWM I/O pin pair. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) R/W-0 R/W-0 R/W-0 ...
Page 164
... DS70265D-page 162 (1) R/W-1 R/W-1 R/W-1 POVD3L POVD2H POVD2L R/W-0 R/W-0 R/W-0 POUT3L POUT2H POUT2L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 POVD1H POVD1L bit 8 R/W-0 R/W-0 POUT1H POUT1L bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 165
... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ...
Page 166
... NOTES: DS70265D-page 164 Preliminary © 2009 Microchip Technology Inc. ...
Page 167
... PCDOUT Existing Pin Logic 0 UPDNx Up/Down 1 © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • 16-bit up/down position counter • Count direction status • Position Measurement (x2 and x4) mode source ...
Page 168
... Timer gated time accumulation disabled DS70265D-page 166 R-0 R/W-0 R/W-0 INDEX UPDN R/W-0 R/W-0 R/W-0 TQCKPS<1:0> POSRES U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 QEIM<2:0> bit 8 R/W-0 R/W-0 TQCS UPDN_SRC bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 169
... UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin state defines position counter direction 0 = Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction Note: When configured for QEI mode, control bit is a ‘don’t care’. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265D-page 167 ...
Page 170
... Unimplemented: Read as ‘0’ DS70265D-page 168 U-0 U-0 R/W-0 — — IMV<2:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 CEID bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 171
... SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Each SPI module consists of a 16-bit shift register, SPIxSR (where 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates status conditions ...
Page 172
... DS70265D-page 170 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 173
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 ...
Page 174
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. DS70265D-page 172 (3) (3) Preliminary © 2009 Microchip Technology Inc. ...
Page 175
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — ...
Page 176
... NOTES: DS70265D-page 174 Preliminary © 2009 Microchip Technology Inc. ...
Page 177
... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 18.1 Operating Modes The hardware fully implements all the master and slave functions of the I specifications, as well as 7-bit and 10-bit addressing ...
Page 178
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...
Page 179
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 180
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70265D-page 178 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master master) Preliminary © 2009 Microchip Technology Inc. ...
Page 181
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/C-0 HS — ...
Page 182
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70265D-page 180 2 C slave device address byte. Preliminary © 2009 Microchip Technology Inc. ...
Page 183
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — ...
Page 184
... NOTES: DS70265D-page 182 Preliminary © 2009 Microchip Technology Inc. ...
Page 185
... FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 • Baud rates ranging from 4 Mbps to 61 bps at 4x mode at 40 MIPS • 4-deep First-In First-Out (FIFO) Transmit Data buffer • ...
Page 186
... DS70265D-page 184 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 187
... Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 MODE REGISTER (CONTINUED) ...
Page 188
... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 189
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 STATUS AND CONTROL REGISTER (CONTINUED) x ...
Page 190
... NOTES: DS70265D-page 188 Preliminary © 2009 Microchip Technology Inc. ...
Page 191
... There is only one sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 Depending on the particular device pinout, the ADC can have up to six analog input pins, designated AN0 through AN5 ...
Page 192
... REF REF 2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation. DS70265D-page 190 Preliminary (1) ( REF DD REF SS ADC1BUF0 ADC1BUF1 ADC1BUF2 V V REFH REFL SAR ADC ADC1BUFE ADC1BUFF © 2009 Microchip Technology Inc. ...
Page 193
... FIGURE 20-2: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ12MC202 DEVICES AN0 AN5 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V - REF CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 V - REF CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 V - REF CH123NA CH123NB AN2 AN5 CH123SA CH123SB (2) CH3 ...
Page 194
... T OSC 2: See the ADC Electrical Characteristics for the exact RC clock value. DS70265D-page 192 ADxCON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 when the PLL is enabled. If the PLL is not used, F OSC = 1/F . OSC Preliminary ADxCON3<15> equal OSC © 2009 Microchip Technology Inc. ...
Page 195
... SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> Samples multiple channels individually in sequence © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 — ...
Page 196
... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in prog- ress. Automatically cleared by hardware at start of a new conversion. DS70265D-page 194 Preliminary © 2009 Microchip Technology Inc. ...
Page 197
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2009 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 — ...
Page 198
... Note 1: This bit only used if AD1CON1<SSRC> This bit is not used if AD1CON3<ADRC> DS70265D-page 196 R/W-0 R/W-0 R/W-0 (1) SAMC<4:0> R/W-0 R/W-0 R/W-0 (2) ADCS<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ( Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 199
... Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 dsPIC33FJ12MC202 devices only: If AD12B = Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 ...
Page 200
... Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 dsPIC33FJ12MC202 devices only: If AD12B = Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 ...