DSPIC33FJ12MC202-I/ML Microchip Technology, DSPIC33FJ12MC202-I/ML Datasheet - Page 45

• Manufacturer Part Number: DSPIC33FJ12MC202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 4-23:
TABLE 4-24:
TABLE 4-25:
RCON
OSCCON
CLKDIV
PLLFBD
OSCTUN
Legend:
Note
NVMCON
NVMKEY
Legend:
Note
PMD1
PMD2
PMD3
Legend:
File Name
File Name
File Name
1:
2:
1:
Addr
0740
0742
0744
0746
0748
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
Addr
0770
0772
0774
0760
0766
SYSTEM CONTROL REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
TRAPR
Bit 15
ROI
IC8MD
Bit 15
Bit 15
—
—
—
WR
—
—
—
IOPUWR
Bit 14
IC7MD
Bit 14
WREN
—
—
Bit 14
—
—
—
COSC<2:0>
DOZE<2:0>
Bit 13
Bit 13
T3MD
WRERR
—
—
—
Bit 13
—
—
—
Bit 12
Bit 12
T2MD
—
—
—
—
—
Bit 12
—
—
DOZEN
Bit 11
T1MD
Bit 11
—
—
—
—
—
—
Bit 11
—
—
QEIMD
Bit 10
Bit 10
—
—
—
—
—
Bit 10
—
—
FRCDIV<2:0>
NOSC<2:0>
PWM1MD
IC2MD
Bit 9
Bit 9
CM
—
—
—
Bit 9
—
—
VREGS
Bit 8
IC1MD
Bit 8
—
—
—
Bit 8
—
—
CLKLOCK IOLOCK
EXTR
I2C1MD
Bit 7
PLLPOST<1:0>
Bit 7
—
—
—
Bit 7
—
Bit 6
SWR
—
Bit 6
ERASE
—
—
—
Bit 6
SWDTEN
LOCK
Bit 5
U1MD
—
Bit 5
—
—
Bit 5
—
PLLDIV<8:0>
WDTO
PWM2MD
Bit 4
—
Bit 4
Bit 4
—
—
NVMKEY<7:0>
—
SLEEP
Bit 3
SPI1MD
CF
Bit 3
Bit 3
—
—
TUN<5:0>
PLLPRE<4:0>
Bit 2
IDLE
—
Bit 2
Bit 2
—
—
—
NVMOP<3:0>
LPOSCEN
Bit 1
BOR
OC2MD
Bit 1
Bit 1
—
—
OSWEN
AD1MD
OC1MD
Bit 0
POR
Bit 0
Bit 0
—
Resets
xxxx
0300
3040
0030
0000
Resets
Resets
0000
0000
0000
0000
0000
All
All
All
(1)
(2)
(1)