DSPIC33FJ12MC202-I/ML Microchip Technology, DSPIC33FJ12MC202-I/ML Datasheet - Page 207

• Manufacturer Part Number: DSPIC33FJ12MC202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 21-2:
21.2
All of the dsPIC33FJ12MC201/202 devices power their
core digital logic at a nominal 2.5V. This can create a
conflict for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33FJ12MC201/202
family incorporate an on-chip regulator that allows the
device to run its core logic from V
The regulator provides power to the core from the other
V
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the V
(Figure 21-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Table 24-13 located in Section 24.1
“DC Characteristics”.
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 21-1:
© 2009 Microchip Technology Inc.
DD
Note:
Note 1:
pins. When the regulator is enabled, a low-ESR
ICS<1:0>
Bit Field
2:
On-Chip Voltage Regulator
C
,
EFC
STARTUP
it takes approximately 20 μs for the on-chip
It is important for low-ESR capacitors to be
placed as close as possible to the V
V
DDCORE
These are typical operating voltages. Refer
to Section TABLE 24-13: “Internal Volt-
age Regulator Specifications” located in
Section 24.1 “DC Characteristics” for the
full operating ranges of V
V
It is important for low-ESR capacitors to be
placed as close as possible to the V
V
3.3V
DDCORE
DDCORE
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
is applied every time the device
pin.
.
pin.
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
V
V
V
DD
CAP
SS
dsPIC33F
STARTUP
/V
DDCORE
Register
FICD
DD
, code execution is
DD
.
CAP
and V
(1)
/V
DDCORE
CAP
CAP
ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
/
/
CAP
Preliminary
pin
/
dsPIC33FJ12MC201/202
21.3
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage V
pose of the BOR module is to generate a device Reset
when a brown-out condition occurs. Brown-out condi-
tions are generally caused by glitches on the AC mains
(for example, missing portions of the AC cycle wave-
form due to bad power transmission lines, or voltage
sags due to excessive current draw when a large
inductive load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should V
DD
BOR: Brown-Out Reset
Description
fall below the BOR threshold voltage.
CAP
/V
DDCORE
DS70265D-page 205
. The main pur-