ATMEGA3290PV-10AUR Atmel, ATMEGA3290PV-10AUR Datasheet - Page 232

• Manufacturer Part Number: ATMEGA3290PV-10AUR
• Description: MCU AVR 32K FLASH 10MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3290PV-10AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.2.5
23.2.6
23.2.7
23.2.8
8021G–AVR–03/11
LCD Contrast Controller/Power Supply
LCDCAP
LCD Buffer Driver
Display requirements
To energize a segment, an absolute voltage above a certain threshold must be applied. This is
done by letting the output voltage on corresponding COM pin and SEG pin have opposite phase.
For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage lev-
els must be applied. Otherwise, non-energized segments on COM0 would be energized for all
non-selected common.
Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0
compared to none addressed COM lines. Non-energized segments are in phase with the
addressed COM0, and energized segments have opposite phase and large amplitude. For
waveform figures refer to
LCDDR0 is multiplexed into the decoder. The decoder is controlled from the LCD timing and
sets up signals controlling the analog switches to produce an output waveform. Next, COM1 is
addressed, and latched data from LCDDR9 - LCDDR5 is input to decoder. Addressing continu-
ous until all COM lines are addressed according to number of common (duty). The display data
are latched before a new frame start.
The peak value (V
by software from 2.6V to 3.35V independent of V
until V
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in
ure
as a reservoir for LCD power (V
the time until V
Figure 23-2. LCDCAP Connection
Intermediate voltage levels are generated from buffers/drivers. The buffers are active the
amount of time specified by LCDDC[2:0] in LCDCCR. Then LCD output pins are tri-stated and
buffers are switched off. Shortening the drive time will reduce power consumption, but displays
with high internal resistance or capacitance may need longer drive time to achieve sufficient
contrast.
When using more than one common pin, the maximum period the LCD drivers can be turned on
for each voltage transition on the LCD pins is 50% of the prescaled LCD clock period, clk
To avoid flickering, it is recommended to keep the framerate above 30Hz, thus giving a maxi-
23-2, if the LCD module is enabled and configured to use internal power. This capacitor acts
LCD
has reached its target value.
LCD
LCD
reaches its target value.
) on the output waveform determines the LCD Contrast. V
”Mode of Operation” on page
LCD
). A large capacitance reduces ripple on V
62
63
64
1
CC
2
. An internal signal inhibits output to the LCD
3
ATmega329P/3290P
233. Latched data from LCDDR4 -
LCD
LCD
but increases
is controlled
LCD_PS
Fig-
232
.