DSPIC30F4011-20E/PT Microchip Technology, DSPIC30F4011-20E/PT Datasheet - Page 14

• Manufacturer Part Number: DSPIC30F4011-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401120EPT

dsPIC30F4011/4012
16. Module: I
DS80454D-page 14
When the I
either in single-master or multi-master mode, the
I
address is detected or not. Therefore, an I
receiver overflow condition occurs and this
condition is indicated by the I2COV flag in the
I2CSTAT register.
This overflow condition inhibits the ability to set the
I
valid data byte is received. Therefore, the I
slave Interrupt Service Routine (ISR) is not called
and the I
receiving the next data byte.
Work arounds
To avoid this issue, either of the following two work
arounds can be implemented, depending on the
application requirements.
Work around 1:
For applications in which the I
is not required, the following procedure can be
used to receive valid data bytes:
1. Wait until the RBF flag is set.
2. Poll the I
3. If SI2CF is not set in the corresponding
4. If the SI2CF is set in the corresponding
5. Read the I2CRCV buffer to recover valid data
6. Clear the I
7. Go back to step 1 to continue receiving
2
2
C receiver buffer is filled whether a valid slave
C receive interrupt flag (SI2CF) when the last
Interrupt Flag Status register (IFSx), a valid
address or data byte has not been received for
the current slave. Execute a dummy read of
the I
the RBF flag. Go back to step 1 until SI2CF is
set and then continue to Step 4.
Interrupt Flag Status register (IFSx), valid data
has been received. Check the D_A flag to
verify that an address or a data byte has been
received.
bytes. This will also clear the RBF flag.
incoming data bytes.
2
C receiver buffer, I2CRCV; this will clear
2
2
C receiver buffer is not read prior
2
2
C
C module is configured as a slave,
C receiver interrupt SI2CIF flag.
2
C receiver interrupt flag SI2CF.
2
C receiver interrupt
2
2
C
C
17. Module: PWM
Work around 2:
Use this work around for applications in which the
I
the RBF and the I2COV flags in the I2CSTAT
register are set due to previous data transfers in
the I2C bus (i.e., between master and other
slaves); the following procedure can be used to
receive valid data bytes:
1. When a valid slave address byte is detected,
2. Check the status of the D_A flag and the
3. If the D_A flag is cleared and the I2COV flag
4. Clear the I2COV flag and perform a dummy
5. Verify that the recovered address byte
6. If the D_A flag and the I2COV flag are both set,
Affected Silicon Revisions
If the PTDIR bit is set (when PTMR is counting
down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
up as if PTDIR was zero.
Work around
None.
Affected Silicon Revisions
2
C receiver interrupt is required. Assuming that
A1
A1
X
X
SI2CF bit is set and the I
service routine is called; however, the RBF and
I2COV bits are already set due to data
transfers between other I
I2COV flag in the I2CSTAT register when exe-
cuting the I
are set, an invalid data byte was received but a
valid address byte was received. The overflow
condition occurred because the I
buffer was overflowing with previous I
transfers between other I
condition only occurs after a valid slave
address was detected.
read of the I
clear the RBF bit and recover the valid address
byte. This action will also avoid the loss of the
next data byte due to an overflow condition.
matches the current slave address byte. If they
match, the next data to be received is a valid
data byte.
a valid data byte was received and a previous
valid data byte was lost. It will be necessary to
code for handling this overflow condition.
A2
A2
X
X
A3
A3
2
X
X
C slave service routine.
2
C receiver buffer, I2CRCV, to
© 2010 Microchip Technology Inc.
A4
A4
X
X
2
C nodes.
2
C slave interrupt
2
C nodes. This
2
C receive
2
C data