ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet

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... PDIP, 44-lead TQFP, and 44-pad MLF • Operating Voltages – 1.8 - 5.5V for ATmega162V – 2.7 - 5.5V for ATmega162 • Speed Grades – MHz for ATmega162V (see – MHz for ATmega162 (see ® 8-bit Microcontroller (1) Figure 113 on page 266) ...

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Pin Figure 1. Pinout ATmega162 Configurations Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is ...

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Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize ...

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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is a powerful microcontroller that provides a highly flexi- ble and cost effective solution to many embedded control applications. ...

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The timed sequence for changing the Watchdog Time-out period is disabled. See Sequences for Changing the Configuration of the Watchdog Timer” on page 56 • The double buffering of the USART Receive Registers is disabled. See AVR UART – ...

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Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins ...

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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ...

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About Code This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before Examples compilation. Be aware that not all C ...

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AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and ...

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Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between ...

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Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable ...

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General Purpose The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve Register File the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand ...

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The X-register, Y- The registers R26..R31 have some added functions to their general purpose usage. These reg- register, and Z-register isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and ...

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Instruction This section describes the general access timing concepts for instruction execution. The AVR Execution Timing CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 6 vard architecture and the fast-access Register File ...

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BOOTRST Fuse, see programming” on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All ...

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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep ; enter sleep, waiting for interrupt ; note: will enter ...

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AVR This section describes the different memories in the ATmega162. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega162 ATmega162 features an EEPROM Memory for data storage. All three ...

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SRAM Data Figure 9 Memory refers to the ATmega161 compatibility mode, configuration A to the non-compatible mode. The ATmega162 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for ...

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Figure 9. Data Memory Map Data Memory Access This section describes the general access timing concepts for internal memory access. The Times internal data SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data ...

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Programming” on page 231 in SPI, JTAG, or Parallel Programming mode. EEPROM Read/Write The EEPROM Access Registers are accessible in the I/O space. Access The write access time for the EEPROM is given in the user software detect when ...

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The EEPROM Data Bit Register – EEDR Read/Write Initial Value • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the ...

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Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register ...

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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The ...

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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...

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I/O Memory The I/O space definition of the ATmega162 is shown in All ATmega162 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 ...

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External Memory With all the features the External Memory Interface provides well suited to operate as an Interface interface to memory devices such as external SRAM and FLASH, and peripherals such as LCD- display, A/D, and D/A. The ...

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The control bits for the External Memory Interface are located in three registers, the MCU Con- trol Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special Function IO Register – SFIOR. When the XMEM interface is ...

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Pull-up and Bus The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port register is Keeper written to one. To reduce power consumption in sleep mode recommended to disable the pull-ups by writing the ...

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Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 System Clock (CLK Note: Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0 Note: 2513K–AVR–07/ CPU ALE A15:8 Prev. ...

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Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1 System Clock (CLK Note: XMEM Register Description MCU Control Register Bit – MCUCR Read/Write Initial Value • Bit 7 – SRE: External SRAM/XMEM Enable Writing SRE ...

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Table 2. Sector Limits with Different Settings of SRL2..0 SRL2 • Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait-state Select Bits for Upper Sector The SRW11 and SRW10 bits control ...

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Special Function IO Bit Register – SFIOR Read/Write Initial Value • Bit 6 – XMBK: External Memory Bus Keeper Enable Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, AD7:0 will ...

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When the device is set in ATmega161 compatibility mode, the internal address space is 1,120 bytes. This implies that the first 1,120 bytes of the external memory can be accessed at addresses 0x8000 to 0x845F. To the Application software, the ...

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Using all 64KB Since the external memory is mapped after the internal memory as shown in Locations of External 64,256 Bytes of external memory are available by default (address space 0x0000 to 0x04FF is Memory reserved for internal memory). However, ...

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System Clock and Clock Options Clock Systems Figure 18 need not be active at a given time. In order to reduce power consumption, the clocks to modules and their not being used can be halted by using different sleep modes, ...

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Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 5. Device ...

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Figure 19. Crystal Oscillator Connections The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:1 as shown in Table 7. Crystal Oscillator Operating Modes CKSEL3:1 100 ...

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... OSCCAL Register and thereby automatically calibrates the RC Oscillator and 25°C, this calibration gives a frequency within ±10% of the nominal frequency. Using cal- ibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±2% accuracy at any given V chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset ...

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Time-out. For more information on the pre-programmed calibration value, see the section bration Byte” on page Table 11. Internal Calibrated RC Oscillator Operating Modes Note: When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown ...

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Table 13. Internal RC Oscillator Frequency Range. OSCCAL Value 0x00 0x3F 0x7F External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 20. To run the device on an external clock, the ...

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Any clock sources, including Internal RC Oscillator, can be selected when PortB 0 serves as clock output. If the system clock prescaler is used the divided system clock that is output when the CKOUT Fuse is programmed. ...

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Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to ...

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Power Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- Management tion to the application’s requirements. and Sleep To ...

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Extended MCU Bit Control Register – EMCUCR Read/Write Initial Value • Bit 7 – SM0: Sleep Mode Select Bit 0 The Sleep Mode Select bits select between the five available sleep modes as shown in 16. Table 16. Sleep Mode ...

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Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR ...

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Minimizing Power There are several issues to consider when trying to minimize the power consumption in an AVR Consumption controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so ...

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... Sources” on page ). POT ) and the Brown-out Detector is enabled. The device is guaranteed to BOT voltage down for details. ATmega162/V Figure 21 shows the Reset 36. is below the Brown-out must be set to the BOT BOT for ATmega162V is 1.8V). BOT “IEEE 1149.1 (JTAG) 47 ...

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Figure 21. Reset Logic BODLEVEL [ 2..0] Table 18. Reset Characteristics Symbol V POT V RST t RST Note: Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR ...

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Figure 22. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL Figure 23. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum ...

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... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. This test is performed using BODLEVEL = 110 for ATmega162V, BODLEVEL = 101 and BODLEVEL = 100 for ATmega162. 2. For ATmega162V. Otherwise reserved. Parameter ...

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Figure 25. Brown-out Reset During Operation TIME-OUT INTERNAL Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the ...

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Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 1 – EXTRF: External ...

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WDT in any of the safety levels. Refer to the Watchdog Timer” on page 56 Table 22. WDT Configuration as a Function of the Fuse Settings of M161C and WDTON. M161C Unprogrammed Unprogrammed Programmed Programmed Figure 27. Watchdog Timer Watchdog ...

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In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, ...

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The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly ...

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Timed Sequences The sequence for changing configuration differs slightly between the three safety levels. Sepa- for Changing the rate procedures are described for each level. Configuration of the Watchdog Timer Safety Level 0 This mode is compatible with the Watchdog ...

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Interrupts This section describes the specifics of the interrupt handling as performed in ATmega162. For a general explanation of the AVR interrupt handling, refer to page 14. grammed, while assembly code examples in this sections are using the interrupt table ...

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Notes: Table 25. Reset and Interrupt Vectors if M161C is programmed Vector No Notes: ATmega162 When ...

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Table 26 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is ...

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When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program ...

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When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...

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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...

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I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI ...

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Figure 29. General Digital I/O Note: Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Description for I/O-Ports” on page PORTxn bits at the PORTx I/O address, and the PINxn bits ...

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Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11 intermediate step. Table 27 Table 27. ...

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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...

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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...

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Unconnected pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should ...

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Table 28 ure 32 the modules having the alternate function. Table 28. Generic Description of Overriding Signals for Alternate Functions. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions ...

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Special Function IO Bit Register – SFIOR Read/Write Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...

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Table 30. Overriding Signals for Alternate Functions in PA7..PA4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE ) DIEOV (3) DI AIO Notes: Table 31. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PUOE PUOV DDOE DDOV PVOE ...

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Alternate Functions Of The Port B pins with alternate functions are shown in Port B Table 32. Port B Pins Alternate Functions Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • ...

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AIN1/TXD1 – Port B, Bit 3 AIN1, Analog Comparator Negative input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. TXD1, ...

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Table 33. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 34. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV ...

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Alternate Functions of The Port C pins with alternate functions are shown in Port C the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be activated even if a reset occurs. Table 35. Port C Pins Alternate Functions Port ...

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A13/TMS/PCINT13 – Port C, Bit 5 A13, External memory interface address bit 13. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not ...

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Table 36. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV (2) DI AIO Notes: Table 37. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV ...

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Alternate Functions of The Port D pins with alternate functions are shown in Port D Table 38. Port D Pins Alternate Functions Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • ...

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TOSC1/XCK0/OC3A – Port D, Bit 4 TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PD4 is disconnected from the port, and becomes the input of the ...

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RXD0 – Port D, Bit 0 RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When USART0 forces this pin to ...

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Alternate Functions of The Port E pins with alternate functions are shown in Port E Table 41. Port E Pins Alternate Functions Port Pin PE2 PE1 PE0 The alternate pin configuration is as follows: • OC1B – Port E, Bit ...

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Register Description for I/O- Ports Port A Data Register – Bit PORTA Read/Write Initial Value Port A Data Direction Bit Register – DDRA Read/Write Initial Value Port A Input Pins Bit Address – PINA Read/Write Initial Value Port B Data ...

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Port C Input Pins Bit Address – PINC Read/Write Initial Value Port D Data Register – Bit PORTD Read/Write Initial Value Port D Data Direction Bit Register – DDRD Read/Write Initial Value Port D Input Pins Bit Address – PIND ...

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External The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2..0 or PCINT15..0 pins are Interrupts configured as outputs. This feature ...

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Table 43. Interrupt 1 Sense Control ISC11 • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the ...

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General Interrupt Bit Control Register – GICR Read/Write Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- ...

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General Interrupt Flag Bit Register – GIFR Read/Write Initial Value • Bit 7 – INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit ...

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Pin Change Mask Bit Register 1 – PCMSK1 Read/Write Initial Value • Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8 Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set ...

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Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: Timer/Counter0 • Single Channel Counter with PWM • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency ...

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The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the Output ...

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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 34 shows a block diagram of the counter and its surroundings. Figure 34. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk ...

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Figure 35. Output Compare Unit, Block Diagram The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...

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Using the Output Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock Compare Unit cycle, there are risks involved when changing TCNT0 when using the output compare channel, independently of whether the ...

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The design of the output compare pin logic allows initialization of the OC0 state before the out- put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. Compare Output Mode The Waveform Generator uses ...

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Figure 37. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be ...

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Figure 38. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast ...

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However, due to the sym- metric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed ...

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The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out- put will be continuously low and if set ...

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Figure 42. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk clk (clk TCNTn OCRn OCFn Figure 43 Figure 43. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) ...

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Timer/Counter Register Description Timer/Counter Control Bit Register – TCCR0 Read/Write Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with ...

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When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Normal or CTC mode (non-PWM). Table 48. Compare Output Mode, non-PWM Mode COM01 Table 49 mode. Table ...

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Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 51. Clock Select Bit Description CS02 external pin ...

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Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is ...

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Timer/Counter0, Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counter1, Timer/Counter3, Timer/Counter1, and Timer/Counter0. and Timer/Counter3 Prescalers Internal Clock Source The Timer/Counter can be clocked directly ...

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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f sampling, the maximum ...

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The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: Timer/Counter • True 16-bit Design (i.e., allows 16-bit PWM) (Timer/Counter • Two Independent Output Compare Units • Double ...

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Figure 46. 16-bit Timer/Counter Block Diagram Note: Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B), and Input Capture Regis- ter (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described ...

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The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICPn the Analog Comparator pins “Analog Comparator” on page Canceler) for reducing the chance of ...

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Accessing 16-bit The TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVR CPU via Registers the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer ...

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The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: ; Save Global Inter?upt ...

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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...

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Timer/Counter The Timer/Counter can be clocked by an internal or an external clock source. The clock source Clock Sources is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter Control ...

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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture ...

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TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written ...

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I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP ...

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Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper eight bits of either the OCRnx buffer or OCRnx Com- pare Register in ...

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Compare Match The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses Output Unit the COMnx1:0 bits for defining the output compare (OCnx) state at the next Compare Match. Secondly the COMnx1:0 bits control the OCnx pin ...

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Compare Output Mode The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. and Waveform For all modes, setting the COMnx1 tells the Waveform Generator that no action on the Generation OCnx Register is ...

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Figure 51. CTC Mode, Timing Diagram An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If ...

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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter ...

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Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ...

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Phase Correct PWM The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3 Mode 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like ...

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TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or ...

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The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA ...

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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...

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Timer/Counter The Timer/Counter is a synchronous design and the timer clock (clk Timing Diagrams clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the ...

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Figure 57. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) TOVn and ICFn (Update at TOP) Figure 58 Figure 58. Timer/Counter Timing Diagram, with Prescaler (f (CTC and FPWM) (PC and PFC PWM) TOVn and ICFn ...

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Timer/Counter Register Description Timer/Counter1 Bit Control Register A – TCCR1A Read/Write Initial Value Timer/Counter3 Bit Control Register A – TCCR3A Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for channel A • Bit 5:4 – COMnB1:0: ...

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Table 54 mode. Table 54. Compare Output Mode, Fast PWM COMnA1/ COMnB1 Note: Table 55 rect or the phase and frequency correct, PWM mode. Table 55. Compare Output Mode, Phase Correct and Phase and Frequency Correct ...

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Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form ...

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Timer/Counter1 Bit Control Register B – TCCR1B Read/Write Initial Value Timer/Counter3 Bit Control Register B – TCCR3B Read/Write Initial Value • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture noise canceler. ...

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Bit 2:0 – CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 55 and Figure Table 57. Clock Select Bit Description Timer/Counter1 CS12 ...

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Timer/Counter1 – Bit TCNT1H and TCNT1L Read/Write Initial Value Timer/Counter3 – Bit TCNT3H and TCNT3L Read/Write Initial Value The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the ...

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The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an output compare interrupt generate a waveform output on the OCnx pin. The Output ...

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Interrupt Vector TIFR, is set. • Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is ...

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TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. • Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is ...

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Extended Bit Timer/Counter Interrupt Flag Register (1) Read/Write – ETIFR Initial Value Note: • Bit 5 – ICF3: Timer/Counter3, Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register ...

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Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: Timer/Counter2 • Single Channel Counter with PWM and • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) Asynchronous ...

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Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac- tive when no clock source is selected. The output from the clock select ...

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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 60 shows a block diagram of the counter and its surrounding environment. Figure 60. Counter Unit Block Diagram Signal description (internal signals): count direction clear ...

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Figure 61. Output Compare Unit, Block Diagram The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is ...

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The Setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal ...

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Compare Output Mode The Waveform Generator uses the COM21:0 bits differently in Normal, CTC, and PWM modes. and Waveform For all modes, setting the COM21 tells the Waveform Generator that no action on the OC2 Generation Register is ...

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Clear Timer on In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manip- Compare Match (CTC) ulate the counter resolution. In CTC mode the counter is cleared to zero when the counter ...

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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21 provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its sin- gle-slope operation. The counter counts ...

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The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer ...

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OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Com- pare Match ...

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Figure 67. Timer/Counter Timing Diagram, with Prescaler (f Figure 68 Figure 68. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f TCNTn Figure 69 Figure 69. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f clk_I/O ...

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Timer/Counter Register Description Timer/Counter Control Bit Register – TCCR2 Read/Write Initial Value • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur- ing compatibility ...

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Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin ...

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Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 64. Table 64. Clock Select Bit Description CS22 Timer/Counter ...

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Asynchronous operation of the Timer/Counter Asynchronous Status Bit Register – ASSR Read/Write Initial Value • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk written to one, Timer/Counter2 is ...

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Asynchronous When Timer/Counter2 operates asynchronously, some considerations must be taken. Operation of • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2 Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock ...

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SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading ...

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Timer/Counter Bit Interrupt Flag Register – TIFR Read/Write Initial Value • Bit 4 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output ...

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Timer/Counter Figure 70. Prescaler for Timer/Counter2 Prescaler clk TOSC1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time ...

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Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega162 and peripheral devices or between several AVR devices. The ATmega162 SPI Peripheral includes the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • ...

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SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the End of Transmission Flag (SPIF). If the SPI ...

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The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO, and ...

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Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK outpu?, all others input ldi out ; Enable SPI, Master, se? clock rate fck/16 ldi out ret SPI_MasterTransmit: ; Start transmission of ?ata (r16) out Wait_Transmit: ; Wait for transmission ?omplete ...

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The following code examples show how to initialize the SPI as a slave and how to perform a sim- ple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 2513K–AVR–07/09 (1) ...

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SS Pin Functionality Slave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the ...

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Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, ...

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SPI Status Register – Bit SPSR Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global ...

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Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 73 and ensuring sufficient time for data ...

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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or ...

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Figure 75. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation ...

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AVR USART vs. AVR The USART is fully compatible with the AVR UART regarding: UART – Compatibility • Bit locations inside all USART Registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver Operation However, the ...

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Internal Clock Internal clock generation is used for the asynchronous and the synchronous master modes of Generation – The operation. The description in this section refers to Baud Rate Generator The USART Baud Rate Register ...

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Double Speed The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect Operation (U2X) for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will ...

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Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid ...

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USART The USART has to be initialized before any communication can take place. The initialization pro- Initialization cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For ...

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More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a fixed setting of the Baud and Control Registers, and for these types of applications the initialization ...

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Sending Frames with If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB 9 Data Bit before the low byte of the character is written to UDR. The following code ...

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The Transmit Complete (TXC) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is automatically ...

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Receiving Frames with The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start Data Bits bit will be sampled at the baud rate or XCK clock, and shifted into ...

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Receiving Frames with If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB 9 Data Bits before reading the low bits from the UDR. This rule applies to the FE, DOR and ...

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The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early ...

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Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the ...

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Figure 79. Start Bit Sampling RxD Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample ...

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Figure 81. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the ...

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Table 71. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) # (Data+Parity Bit) Table 72. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) # (Data+Parity Bit) The recommendations of the ...

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If a particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. Using MPCM For an MCU to ...

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Accessing The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some UBRRH/ special consideration must be taken when accessing this I/O location. UCSRC Registers Write Access When doing a write access of this I/O location, the ...

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Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. How- ever, in most applications rarely necessary to read any of these registers. The read access is controlled by a ...

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USART Register Description USART I/O Data Bit Register – UDR Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit ...

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Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is ...

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Bit 4 – RXEN: Receiver Enable Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper- ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the ...

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USART Control and Bit Status Register C – (1) UCSRC Read/Write Initial Value Note: • Bit 7 – URSEL: Register Select This bit selects between accessing the UCSRC or the UBRRH Register read as one when reading UCSRC. ...

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Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char- acter Size frame the receiver and transmitter use. Table 76. UCSZ Bits Settings UCSZ2 ...

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Bit 11:0 – UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART ...

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Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...

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Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 ...

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Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...

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Analog The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin Comparator AIN1, the Analog Comparator Output, ...

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Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit ...

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... JTAG Interface” on page 250 204, respectively. The On-chip Debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Figure 83 TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (Shift Register) between the TDI – ...

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The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. ...

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Figure 84. TAP Controller State Diagram 1 0 2513K–AVR–07/09 Test-Logic-Reset 0 1 Run-Test/Idle Select-DR Scan 1 Capture-DR Shift-DR Exit1-DR Pause-DR 0 Exit2-DR Update-DR 1 ATmega162/V 1 Select-IR Scan Capture- Shift- Exit1-IR ...

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TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary- scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in sition) at the time of the rising edge ...