ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 322

• Manufacturer Part Number: ATMEGA162V-8PU
• Description: IC AVR MCU 16K 8MHZ 1.8V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

iv
ATmega162/V
Analog Comparator 195
JTAG Interface and On-chip Debug System 197
IEEE 1149.1 (JTAG) Boundary-scan 204
Boot Loader Support – Read-While-Write Self-programming 217
Memory Programming 231
Features 197
Overview 197
Test Access Port – TAP 197
TAP Controller 200
Using the Boundary-scan Chain 200
Using the On-chip Debug system 201
On-chip debug specific JTAG instructions 202
On-chip Debug Related Register in I/O Memory 202
Using the JTAG Programming Capabilities 202
Bibliography 203
Features 204
System Overview 204
Data Registers 205
Boundary-scan Specific JTAG Instructions 206
Boundary-scan Chain 208
ATmega162 Boundary-scan Order 213
Boundary-scan Description Language Files 216
Features 217
Application and Boot Loader Flash Sections 217
Read-While-Write and No Read-While-Write Flash Sections 217
Boot Loader Lock Bits 219
Entering the Boot Loader Program 221
Addressing the Flash During Self-programming 223
Self-programming the Flash 224
Program And Data Memory Lock Bits 231
Fuse Bits 232
Signature Bytes 234
Calibration Byte 234
Parallel Programming Parameters, Pin Mapping, and Commands 234
Parallel Programming 236
Serial Downloading 245
SPI Serial Programming Pin Mapping 245
Programming via the JTAG Interface 250
2513K–AVR–07/09