ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 53

• Manufacturer Part Number: ATMEGA162V-8PU
• Description: IC AVR MCU 16K 8MHZ 1.8V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Watchdog Timer
Control Register –
WDTCR
2513K–AVR–07/09
WDT in any of the safety levels. Refer to
the Watchdog Timer” on page 56
Table 22. WDT Configuration as a Function of the Fuse Settings of M161C and WDTON.
Figure 27. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega162 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. In Safety Levels 1 and 2, this bit
must also be set when changing the prescaler bits.
Configuration of the Watchdog Timer” on page 56.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
Bit
Read/Write
Initial Value
M161C
Unprogrammed
Unprogrammed
Programmed
Programmed
R
7
–
0
WDTON
Unprogrammed
Programmed
Unprogrammed
Programmed
R
6
–
0
OSCILLATOR
WATCHDOG
R
5
–
0
for details.
Safety
Level
1
2
0
2
WDCE
R/W
4
0
“Timed Sequences for Changing the Configuration of
WDT
Initial
State
Disabled
Enabled
Disabled
Enabled
WDE
R/W
3
0
See “Timed Sequences for Changing the
How to Disable
the WDT
Timed sequence
Always enabled
Timed sequence
Always enabled
WDP2
R/W
2
0
WDP1
R/W
1
0
ATmega162/V
WDP0
R/W
How to
Change Time-
out
Timed
sequence
Timed
sequence
No restriction
Timed
sequence
0
0
WDTCR
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