ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 80

• Manufacturer Part Number: ATMEGA162V-8PU
• Description: IC AVR MCU 16K 8MHZ 1.8V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

80
ATmega162/V
• RXD0 – Port D, Bit 0
RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver is enabled this
pin is configured as an input regardless of the value of DDD0. When USART0 forces this pin to
be an input, the pull-up can still be controlled by the PORTD0 bit.
Table 39
Figure 32 on page
Table 39. Overriding Signals for Alternate Functions PD7..PD4
Table 40. Overriding Signals for Alternate Functions in PD3..PD0
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
and
Table 40
PD3/INT1
0
0
0
0
0
0
INT1 ENABLE
1
INT1 INPUT/
ICP1 INPUT
–
PD7/RD
SRE
0
SRE
1
SRE
RD
0
0
–
–
68.
relate the alternate functions of Port D to the overriding signals shown in
PD6/WR
SRE
0
SRE
1
SRE
WR
0
0
–
–
PD2/INT0/XCK1
0
0
0
0
XCK1 OUTPUT ENABLE
XCK1
INT0 ENABLE
1
INT0 INPUT/XCK1 INPUT
–
PD5/TOSC2/OC1A
0
0
OC1A
0
–
AS2
AS2
OC1A ENABLE
AS2
T/C2 OSC OUTPUT
PD1/TXD0
TXEN0
0
TXEN0
1
TXEN0
TXD0
0
0
–
–
PD4/TOSC1/XCK0/OC3A
AS2
0
AS2
0
XCK0 OUTPUT ENABLE |
OC3A ENABLE
if
else
AS2
0
XCK0 INPUT
T/C2 OSC INPUT
(XCK0 OUTPUT
ENABLE) then
XCK0 OUTPUT
OC3A
PD0/RXD0
RXEN0
PORTD0 • PUD
RXEN0
0
0
0
0
0
RXD0
–
2513K–AVR–07/09