ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 116

• Manufacturer Part Number: ATMEGA162V-8PU
• Description: IC AVR MCU 16K 8MHZ 1.8V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Force Output
Compare
Compare Match
Blocking by TCNTn
Write
Using the Output
Compare Unit
116
ATmega162/V
updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,
the high byte will be copied into the upper eight bits of either the OCRnx buffer or OCRnx Com-
pare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to
on page
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOCnx) bit. Forcing Compare Match will not set the
OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare
Match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or
toggled).
All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the
same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.
Since writing TCNTn in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNTn when using any of the output compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect wave-
form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP
values. The Compare Match for the TOP will be ignored and the counter will continue to
0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is down-
counting.
The setup of the OCnx should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-
pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
Changing the COMnx1:0 bits will take effect immediately.
109.
“Accessing 16-bit Registers”
2513K–AVR–07/09