STM8S103F2P3TR

Manufacturer Part NumberSTM8S103F2P3TR
DescriptionMCU 8BIT 4K FLASH 20TSSOP
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S103F2P3TR datasheet
 

Specifications of STM8S103F2P3TR

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o16
Program Memory Size4KB (4K x 8)Program Memory TypeFLASH
Eeprom Size640 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 5x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 125°C
Package / Case20-TSSOPProcessor SeriesSTM8S10x
CoreSTM83rd Party Development ToolsEWSTM8
Development Tools By SupplierSTICE-SYS001Lead Free Status / RoHS StatusLead free / RoHS Compliant
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STM8S103K3 STM8S103F3 STM8S103F2
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data
LQFP32 7x7
TSSOP20
SO20W 300 mils
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set
Memories
Program memory: 8 Kbytes Flash; data retention
20 years at 55 °C after 10 kcycles
Data memory: 640 bytes true data EEPROM;
endurance 300 kcycles
RAM: 1 Kbytes
Clock, reset and supply management
2.95 to 5.5 V operating voltage
Flexible clock control, 4 master clock sources:
-
Low power crystal resonator oscillator
-
External clock input
-
Internal, user-trimmable 16 MHz RC
-
Internal low power 128 kHz RC
Clock security system with clock monitor
Power management:
-
Low power modes (wait, active-halt, halt)
-
Switch-off peripheral clocks individually
September 2010
EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
Permanently active, low consumption power-on
and power-down reset
Interrupt management
Nested interrupt controller with 32 interrupts
UFQFPN32 5x5
Up to 27 external interrupts on 6 vectors
Timers
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
UFQFPN20 3x3
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
Window watchdog and independent watchdog
timers
Communications interfaces
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
2
I
C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit, ±1 LSB ADC with up to 5 multiplexed
channels, scan mode and analog watchdog
I/Os
Up to 28 I/Os on a 32-pin package including 21
high sink outputs
Highly robust I/O design, immune against current
injection
Development support
-
Embedded single wire interface module
(SWIM) for fast on-chip programming and
non intrusive debugging
Unique ID
96-bit unique key for each device
DocID15441 Rev 6
1/113
www.st.com

STM8S103F2P3TR Summary of contents

  • Page 1

    STM8S103K3 STM8S103F3 STM8S103F2 Access line, 16 MHz STM8S 8-bit MCU Kbytes Flash, data LQFP32 7x7 TSSOP20 SO20W 300 mils Features Core • 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline • Extended instruction set ...

  • Page 2

    Contents Contents 1 Introduction ..............................................................................................................8 2 Description ...............................................................................................................9 3 Block diagram ........................................................................................................10 4 Product overview ...................................................................................................11 4.1 Central processing unit STM8 .....................................................................................11 4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11 4.3 Interrupt controller .......................................................................................................12 4.4 Flash program ...

  • Page 3

    STM8S103K3 STM8S103F3 STM8S103F2 9 Unique ID ................................................................................................................47 10 Electrical characteristics ....................................................................................48 10.1 Parameter conditions .................................................................................................48 10.1.1 Minimum and maximum values .........................................................48 10.1.2 Typical values .....................................................................................48 10.1.3 Typical curves ....................................................................................48 10.1.4 Loading capacitor ...............................................................................48 10.1.5 Pin input voltage .................................................................................49 10.2 Absolute ...

  • Page 4

    List of tables List of tables Table 1. STM8S103xx access line features .............................................................................................9 Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14 Table 3. TIM timer features ....................................................................................................................16 Table 4. Legend/abbreviations for pinout tables ...................................................................................19 Table 5. UFQFPN32/LQFP32 ...

  • Page 5

    STM8S103K3 STM8S103F3 STM8S103F2 Table 48. EMS data ................................................................................................................................88 Table 49. EMI data .................................................................................................................................88 Table 50. ESD absolute maximum ratings .............................................................................................89 Table 51. Electrical sensitivities .............................................................................................................90 Table 52. 32-pin low profile quad flat package mechanical data ............................................................91 Table 53. 32-lead, ultra ...

  • Page 6

    List of figures List of figures Figure 1. Block diagram .........................................................................................................................10 Figure 2. Flash memory organization ....................................................................................................13 Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................19 Figure 4. STM8S103Fx TSSOP20/SO20 pinout ....................................................................................22 Figure 5. STM8S103Fx UFQFPN20-pin pinout .....................................................................................23 Figure 6. Memory map ...........................................................................................................................26 ...

  • Page 7

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 48. 20-pin, 4.40 mm body, 0.65 mm pitch ...................................................................................97 Figure 49. 20-lead, plastic small outline (300 mils) package .................................................................97 Figure 50. Recommended footprint for on-board emulation ..................................................................98 Figure 51. Recommended footprint without on-board emulation ...........................................................99 Figure ...

  • Page 8

    Introduction 1 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference ...

  • Page 9

    STM8S103K3 STM8S103F3 STM8S103F2 2 Description The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the ...

  • Page 10

    Block diagram 3 Block diagram Reset block Reset POR Single wire Debug/SWIM debug interf. 400 Kbit/s 8 Mbit/s LIN master SPI emul channels 1/2/4 kHz beep 10/113 Figure 1: Block diagram Clock controller Reset Detector BOR Clock ...

  • Page 11

    STM8S103K3 STM8S103F3 STM8S103F2 4 Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central ...

  • Page 12

    Product overview SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging ...

  • Page 13

    STM8S103K3 STM8S103F3 STM8S103F2 program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Data EEPROM memory Low density Flash program memory   (8 Kbytes) Read-out protection (ROP) The read-out protection blocks reading ...

  • Page 14

    Product overview - MHz high-speed user-external clock (HSE user-ext MHz high-speed internal RC oscillator (HSI) - 128 kHz low-speed internal RC (LSI) • Startup clock: After reset, the microcontroller restarts by default with an internal ...

  • Page 15

    STM8S103K3 STM8S103F3 STM8S103F2 Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to ...

  • Page 16

    Product overview • Break input to force the timer outputs into a defined state • Three complementary outputs with adjustable dead time • Encoder mode • Interrupt sources input capture/output compare overflow/update break 4.11 ...

  • Page 17

    STM8S103K3 STM8S103F3 STM8S103F2 • Analog watchdog capability with programmable upper and lower thresholds • Analog watchdog interrupt • External trigger input • Trigger from TIM1 TRGO • End of conversion (EOC) interrupt 4.14 Communication interfaces The following communication interfaces are ...

  • Page 18

    Product overview LIN master mode • Emission: Generates 13-bit synch break frame • Reception: Detects 11-bit break frame 4.14.2 SPI • Maximum speed: 8 Mbit/s (f • Full duplex synchronous transfers • Simplex synchronous transfers on two lines with a ...

  • Page 19

    STM8S103K3 STM8S103F3 STM8S103F2 5 Pinout and pin description Type Level Output speed Port and control configuration Reset state 5.1 STM8S103Kx UFQFPN32/LQFP32 pinout and pin description Table 4: Legend/abbreviations for pinout tables I= Input Output Power supply ...

  • Page 20

    Pinout and pin description 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice ...

  • Page 21

    STM8S103K3 STM8S103F3 STM8S103F2 Input Pin Pin Type no. name floating 15 PB1/AIN1/ I/O X TIM1_CH2N 16 PB0/AIN0/ I/O X TIM1_CH1N 17 PE5/ I/O X SPI_NSS 18 PC1/ I/O X TIM1_CH1/ UART1_CK 19 PC2/ I/O X TIM1_CH2 20 PC3/ I/O X ...

  • Page 22

    Pinout and pin description Input Pin Pin Type no. name floating 28 PD3/ I/O X TIM2_CH2/ ADC_ETR 29 PD4/BEEP/ I/O X TIM2_CH1 30 PD5/ I/O X UART1_TX 31 PD6/ I/O X UART1_RX 32 PD7/ TLI I/O X [TIM1_CH4] (1) I/O ...

  • Page 23

    STM8S103K3 STM8S103F3 STM8S103F2 1. HS high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not ...

  • Page 24

    Pinout and pin description 5.2.3 STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description Pin no. Pin name TSSOP/SO20 UFQFPN20 1 18 PD4/ BEEP/ TIM2_ CH1/ UART1 _CK 2 19 PD5/ AIN5/ UART1 _TX 3 20 PD6/ AIN6/ UART1 _RX 4 1 NRST (2) 5 ...

  • Page 25

    STM8S103K3 STM8S103F3 STM8S103F2 (1) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings. (2) When the MCU is in halt/active-halt mode, PA1 ...

  • Page 26

    Memory and register map 6 Memory and register map 6.1 Memory map 26/113 STM8S103K3 STM8S103F3 STM8S103F2 Figure 6: Memory map 0x00 0000 RAM (1 Kbyte) 513 bytes stack 0x00 03FF 0x00 0800 Reserved 0x00 3FFF 0x00 4000 640 bytes data ...

  • Page 27

    STM8S103K3 STM8S103F3 STM8S103F2 6.2 Register map 6.2.1 I/O port hardware register map Address Block 0x00 5000 0x00 5001 0x00 5002 Port A 0x00 5003 0x00 5004 0x00 5005 0x00 5006 0x00 5007 Port B 0x00 5008 0x00 5009 0x00 500A ...

  • Page 28

    Memory and register map Address Block 0x00 5018 Port E 0x00 5019 0x00 501A Port F 0x00 501B 0x00 501C 0x00 501D 6.2.2 General hardware register map Address Block 0x00 501E to Reserved area (60 bytes) 0x00 5059 0x00 505A ...

  • Page 29

    STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash 0x00 5065 to Reserved area (59 bytes) 0x00 509F 0x00 50A0 ITC 0x00 50A1 0x00 50A2 to Reserved area (17 bytes) 0x00 50B2 0x00 50B3 RST ...

  • Page 30

    Memory and register map Address Block 0x00 50CA 0x00 50CB 0x00 50CC 0x00 50CD 0x00 50CE to Reserved area (3 bytes) 0x00 50D0 0x00 50D1 WWDG 0x00 50D2 0x00 50D3 to 00 Reserved area (13 bytes) 50DF 0x00 50E0 IWDG ...

  • Page 31

    STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 50F4 to Reserved area (12 bytes) 0x00 50FF 0x00 5200 SPI 0x00 5201 0x00 5202 0x00 5203 0x00 5204 0x00 5205 0x00 5206 0x00 5207 0x00 5208 to Reserved area (8 bytes) 0x00 520F ...

  • Page 32

    Memory and register map Address Block 0x00 5218 0x00 5219 0x00 521A 0x00 521B 0x00 521C 0x00 521D 0x00 521E 0x00 521F to Reserved area (17 bytes) 0x00 522F 0x00 5230 UART1 0x00 5231 0x00 5232 0x00 5233 0x00 5234 ...

  • Page 33

    STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 523B to Reserved area (21 bytes) 0x00 523F 0x00 5250 TIM1 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 ...

  • Page 34

    Memory and register map Address Block 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5266 0x00 5267 0x00 5268 0x00 5269 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F ...

  • Page 35

    STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A 0x00 530B 0x00 530C 0x00 530D 0x00 530E 0x00 530F 0x00 5310 0x00 5311 Register ...

  • Page 36

    Memory and register map Address Block 0x00 5312 0x00 5313 0x00 5314 0x00 5315 0x00 5316 0x00 5317 to Reserved area (43 bytes) 0x00 533F 0x00 5340 TIM4 0x00 5341 0x00 5342 0x00 5343 0x00 5344 0x00 5345 0x00 5346 ...

  • Page 37

    STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 5400 ADC1 0x00 5401 0x00 5402 0x00 5403 0x00 5404 0x00 5405 0x00 5406 0x00 5407 0x00 5408 0x00 5409 0x00 540A 0x00 540B 0x00 540C 0x00 540D 0x00 540E 0x00 540F Register label ...

  • Page 38

    Memory and register map Address Block 0x00 5410 to Reserved area (1008 bytes) 0x00 57FF (1) Depends on the previous reset source. (2) Write only register. 6.2.3 CPU/SWIM/debug module/interrupt controller registers Table 9: CPU/SWIM/debug module/interrupt controller registers Address Block 0x00 ...

  • Page 39

    STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 7F75 0x00 7F76 0x00 7F77 0x00 7F78 to 0x00 7F79 0x00 7F80 SWIM 0x00 7F81 to 0x00 7F8F 0x00 7F90 0x00 7F91 0x00 7F92 0x00 7F93 0x00 7F94 0x00 7F95 DM 0x00 7F96 0x00 ...

  • Page 40

    Interrupt vector mapping 7 Interrupt vector mapping IRQ Source Description no. block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 AWU Auto wake up from halt 2 CLK Clock controller 3 EXTI0 Port A external interrupts ...

  • Page 41

    STM8S103K3 STM8S103F3 STM8S103F2 IRQ Source Description no. block 23 TIM4 TIM4 update/ overflow 24 Flash EOP/WR_PG_DIS (1) Except PA1 Wakeup from halt mode - - Reserved DocID15441 Rev 6 Interrupt vector mapping Wakeup from Vector address active-halt mode - 0x00 ...

  • Page 42

    Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each ...

  • Page 43

    STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. OPT1 OPT2 OPT3 Description Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Page 0 defined ...

  • Page 44

    Option bytes Option byte no. OPT4 OPT5 8.1 Alternate function remapping bits Table 13: STM8S103K alternate function remapping bits for 32-pin devices Option byte no. OPT2 44/113 STM8S103K3 STM8S103F3 STM8S103F2 Description 0: No reset generated on halt if WWDG active ...

  • Page 45

    STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. (1) Do not use more than one remapping option in the same port forbidden to enable both AFR1 and AFR0. (2) Refer to pinout description. Table 14: STM8S103F alternate function remapping bits ...

  • Page 46

    Option bytes Option byte no. (1) Refer to pinout description. (2) Do not use more than one remapping option in the same port forbidden to enable both AFR1 and AFR0. 46/113 STM8S103K3 STM8S103F3 STM8S103F2 Description Reserved AFR1 Alternate ...

  • Page 47

    STM8S103K3 STM8S103F3 STM8S103F2 9 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by ...

  • Page 48

    Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

  • Page 49

    STM8S103K3 STM8S103F3 STM8S103F2 10.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to ...

  • Page 50

    Electrical characteristics Symbol Ratings I VDD Total current into V I Total current out of V VSS I IO Output current sunk by any I/O and control pin Output current source by any I/Os and control pin (3) (4) I ...

  • Page 51

    STM8S103K3 STM8S103F3 STM8S103F2 10.3 Operating conditions Symbol Parameter f Internal CPU clock frequency CPU V Standard operating voltage DD VCAP C : capacitance of EXT external capacitor ESR of external (1) capacitor ESL of external (1) capacitor ( ...

  • Page 52

    Electrical characteristics (2) To calculate use the formula P Dmax A value for T given in the previous table and the value for Θ Jmax (3) Τ is given by the test limit. Above this value the ...

  • Page 53

    STM8S103K3 STM8S103F3 STM8S103F2 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as described in 10.3.2.1 Total current consumption in run mode The MCU is placed under ...

  • Page 54

    Electrical characteristics Symbol Parameter Conditions f CPU 2 MHz f CPU Supply current 125 kHz in run mode, I DD(RUN) code executed f CPU from Flash 15.625 kHz f CPU 128 kHz (1) Data based on characterization results, not tested ...

  • Page 55

    STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Conditions 128 = 125 kHz f CPU 128 = 15.625 kHz f CPU 128 kHz (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.2 ...

  • Page 56

    Electrical characteristics Symbol Parameter Conditions (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.3 Total current consumption in active halt mode Table 25: Total current consumption in active halt ...

  • Page 57

    STM8S103K3 STM8S103F3 STM8S103F2 Conditions Main Symbol Parameter voltage regulator (MVR) Supply current I in active halt DD(AH) mode Off Supply current I in active halt DD(AH) mode (1) Data based on characterization results, not tested in production (2) Configured by ...

  • Page 58

    Electrical characteristics 10.3.2.4 Total current consumption in halt mode Table 27: Total current consumption in halt mode at V Symbol Parameter Supply current in halt mode I DD(H) (1) Data based on characterization results, not tested in production Table 28: ...

  • Page 59

    STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Wakeup time active halt mode to run (3) mode Wakeup time active halt mode to run (3) mode Wakeup time from halt mode to run t WU(H) (3) mode (1) Data guaranteed by design, not ...

  • Page 60

    Electrical characteristics HSI internal RC/f Symbol Parameter I DD(TIM1) TIM1 supply current I DD(TIM2) TIM2 supply current I DD(TIM4) TIM4 timer supply current I DD(UART1) UART1 supply current I DD(SPI) SPI supply current DD ...

  • Page 61

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 11: Typ I Figure 12: Typ I vs. V HSE user external clock, f DD(RUN) DD vs. f HSE user external clock, V DD(RUN) CPU DocID15441 Rev 6 Electrical characteristics = 16 MHz CPU = 5 ...

  • Page 62

    Electrical characteristics Figure 13: Typ I Figure 14: Typ I 62/113 STM8S103K3 STM8S103F3 STM8S103F2 vs. V HSI RC osc, f DD(RUN) DD vs. V HSE user external clock, f DD(WFI) DD DocID15441 Rev MHz CPU = 16 ...

  • Page 63

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 15: Typ I Figure 16: Typ I 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for V Table 32: HSE user external clock characteristics Symbol Parameter f User ...

  • Page 64

    Electrical characteristics (1) Data based on characterization results, not tested in production. V HSEH V HSEL HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in ...

  • Page 65

    STM8S103K3 STM8S103F3 STM8S103F2 ( approximately equivalent crystal Cload. (2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value. Refer to crystal manufacturer for more ...

  • Page 66

    Electrical characteristics Symbol Parameter ACC Accuracy of HSI HSI oscillator Accuracy of HSI oscillator (factory calibrated) t HSI oscillator su(HSI) wakeup time including calibration I HSI oscillator DD(HSI) power consumption (1) Refer to application note. (2) Data based on characterization ...

  • Page 67

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 20: Typical HSI frequency variation vs V Low speed internal RC oscillator (LSI) Subject to general operating conditions for V Symbol Parameter f Frequency LSI t LSI oscillator wake-up time su(LSI) I LSI oscillator power consumption ...

  • Page 68

    Electrical characteristics 10.3.5 Memory characteristics RAM and hardware registers Symbol Parameter V Data retention mode RM (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset hardware registers (only in halt mode). ...

  • Page 69

    STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Data retention (data memory) after 300k erase/write cycles +125 ° Supply current (Flash DD programming or erasing for 1 to 128 bytes) (1) Data based on characterization results, not tested ...

  • Page 70

    Electrical characteristics Symbol Parameter I lkg ana Analog input leakage current I lkg(inj) Leakage current in adjacent I/O (1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. (2) Data based on characterisation results, ...

  • Page 71

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 24: Typical pull-up current vs V Symbol Parameter Output low level with 8 pins sunk V OL Output low level with 4 pins sunk Output high level with 8 pins sourced V OH Output high level ...

  • Page 72

    Electrical characteristics (1) Data based on characterization results, not tested in production Symbol Parameter Output low level with 8 pins sunk V OL Output low level with 4 pins sunk V OL Output low level with 4 pins sunk Output ...

  • Page 73

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 27: Typ. V Figure 26: Typ 3.3 V (standard ports (true open drain ports DocID15441 Rev 6 Electrical characteristics 73/113 ...

  • Page 74

    Electrical characteristics Figure 28: Typ. V 74/113 STM8S103K3 STM8S103F3 STM8S103F2 @ V = 3.3 V (true open drain ports Figure 29: Typ (high sink ports DocID15441 Rev 6 ...

  • Page 75

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 30: Typ Figure 31: Typ DocID15441 Rev 6 Electrical characteristics = 3.3 V (high sink ports (standard ports) DD 75/113 ...

  • Page 76

    Electrical characteristics Figure 32: Typ. V 76/113 - Figure 33: Typ DocID15441 Rev 6 STM8S103K3 STM8S103F3 STM8S103F2 = 3.3 V (standard ports (high sink ...

  • Page 77

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 34: Typ. V 10.3.7 Reset pin characteristics Subject to general operating conditions for V Symbol Parameter V IL(NRST) NRST input low (1) level voltage V IH(NRST) NRST input high level voltage V OL(NRST) NRST output low ...

  • Page 78

    Electrical characteristics Symbol Parameter t OP(NRST) NRST output (3) pulse (1) Data based on characterization results, not tested in production. (2) The R pull-up equivalent resistor is based on a resistive transistor PU (3) Data guaranteed by design, not tested ...

  • Page 79

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 37: Typical NRST pull-up current vs V The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the ...

  • Page 80

    Electrical characteristics Symbol Parameter f 1/ SPI clock SCK t frequency c(SCK SCK SCK t c(SCK) t SPI clock rise and r(SCK) t fall time f(SCK) (3) t NSS setup time su(NSS) (3) t NSS hold time ...

  • Page 81

    STM8S103K3 STM8S103F3 STM8S103F2 (1) Parameters are given by selecting 10 MHz I/O output frequency. (2) Data characterization in progress. (3) Values based on design simulation and/or characterization results, and not tested in production. (4) Min time is for the minimum ...

  • Page 82

    Electrical characteristics NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO INP UT MOSI OUTUT 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 2 10.3 interface characteristics Symbol Parameter ...

  • Page 83

    STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter t STOP condition setup time su(STO) t STOP to START condition time w(STO:ST A) (bus free) C Capacitive load for each bus line b ( must be at least 8 MHz to achieve ...

  • Page 84

    Electrical characteristics Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN C Internal sample and hold ADC capacitor (1) t Minimum sampling time S t Wake-up time from standby STAB t Minimum total conversion time CONV (including ...

  • Page 85

    STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter |E | Gain error Differential linearity error Integral linearity error L (1) Data based on characterization results, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting ...

  • Page 86

    Electrical characteristics Symbol Parameter |E | Gain error Differential linearity error Integral linearity error L (1) Data based on characterization results, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative ...

  • Page 87

    STM8S103K3 STM8S103F3 STM8S103F2 3. End point correlation line E = Total unadjusted error: maximum deviation between the actual and the ideal transfer T curves Offset error: deviation between the first actual transition and the first ideal one. O ...

  • Page 88

    Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress ...

  • Page 89

    STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter SAE EMI level (1) Data based on characterisation results, not tested in production. 10.3.11.4 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is ...

  • Page 90

    ... Parameter LU Static latch-up class (1) Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 90/113 ...

  • Page 91

    STM8S103K3 STM8S103F3 STM8S103F2 11 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ...

  • Page 92

    Package information Dim. mm Min D3 E 8.800 E1 6.800 0.450 L1 k 0.0° ccc (1) Values in inches are converted from mm and rounded to 4 decimal digits 92/113 STM8S103K3 STM8S103F3 STM8S103F2 inches Typ Max Min ...

  • Page 93

    STM8S103K3 STM8S103F3 STM8S103F2 11.2 32-lead UFQFPN package mechanical data Figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package ( Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to ...

  • Page 94

    Package information Dim. mm Min b 0.180 D 4.850 D2 3.200 E 4.850 E2 3.200 e L 0.300 ddd (1) Values in inches are converted from mm and rounded to 4 decimal digits. 11.3 20-lead UFQFPN package mechanical data Figure ...

  • Page 95

    STM8S103K3 STM8S103F3 STM8S103F2 Table 54: 20-lead, ultra thin, fine pitch quad flat no-lead package ( package Dim. mm Min 0.500 A1 0.000 0.500 L2 0.300 0.180 ddd 0.050 (1) ...

  • Page 96

    Package information 11.4 20-pin TSSOP package mechanical data aaa CP A Table 55: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data Dim. mm Min A A1 0.050 A2 0.800 b 0.190 c 0.090 D 6.400 E 6.200 E1 4.300 ...

  • Page 97

    STM8S103K3 STM8S103F3 STM8S103F2 Dim. mm Min k 0.0° aaa (1) Values in inches are converted from mm and rounded to 4 decimal digits 11.5 20-pin SO package mechanical data Figure 49: 20-lead, plastic small outline (300 mils) package Table 56: ...

  • Page 98

    Package information Dim. mm Min H 10.000 h 0.250 L 0.400 k 0.0° ddd (1) Values in inches are converted from mm and rounded to 4 decimal digits 11.6 UFQFPN recommended footprint Figure 50: Recommended footprint for on-board emulation 1. ...

  • Page 99

    STM8S103K3 STM8S103F3 STM8S103F2 Figure 51: Recommended footprint without on-board emulation 1. Drawing is not to scale 2. Dimensions are in millimeters DocID15441 Rev 6 Package information 99/113 ...

  • Page 100

    Thermal characteristics 12 Thermal characteristics The maximum chip junction temperature (T Operating conditions. The maximum chip-junction temperature, T the following equation Jmax Amax Where: • the maximum ambient temperature in °C Amax • ...

  • Page 101

    STM8S103K3 STM8S103F3 STM8S103F2 12.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 12.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order ...

  • Page 102

    Ordering information 13 Ordering information Figure 52: STM8S103x access line ordering information scheme Example: Product class STM8 microcontroller Family type S = Standard Sub-family type 10x = Access line 103 sub-family Pin count pins ...

  • Page 103

    ... LQFP32: 2 lines of 7 characters max: " _" and " _" TSSOP20/SO20: 1 line of 10 characters max: " _" Three characters are reserved for code identification. Temperature range [ ] -40°C to +85° -40°C to +125°C Padding value for unused program memory (check only one option) [ ]0xFF a FASTROM code name is assigned by STMicroelectronics. ............................................................................................. ............................................................................................. ............................................................................................. ............................................................................................. a ............................................................................................. 4 Kbyte ...

  • Page 104

    Ordering information [ ]0x83 [ ]0x75 OPT0 memory readout protection (check only one option Disable Enable OPT1 user boot code area (UBC) 0x(_ _) fill in the hexadecimal value, refering to the datasheet and the ...

  • Page 105

    STM8S103K3 STM8S103F3 STM8S103F2 AFR3 AFR4 AFR5 (check only one option) AFR6 (check only one option) AFR7 OPT2 alternate function remapping for STM8S103F Do not use more than one remapping option in the same port forbidden to enable both ...

  • Page 106

    Ordering information OPT3 watchdog WWDG_HALT (check only one option) WWDG_HW (check only one option) IWDG_HW (check only one option) LSI_EN (check only one option) HSITRIM (check only one option) OPT4 wakeup PRSC (check only one option) CKAWUSEL (check only one ...

  • Page 107

    STM8S103K3 STM8S103F3 STM8S103F2 Date: Signature: ........................................................................................................... ........................................................................................................... DocID15441 Rev 6 Ordering information 107/113 ...

  • Page 108

    ... In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. ...

  • Page 109

    STM8S103K3 STM8S103F3 STM8S103F2 14.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring • Seamless ...

  • Page 110

    Revision history 15 Revision history Date Revision 02-Mar-2009 1 10-Apr-2009 2 10-Jun-2009 3 110/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 58: Document revision history Changes Initial revision Added Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. Updated Auto wakeup counter. ...

  • Page 111

    STM8S103K3 STM8S103F3 STM8S103F2 Date Revision 16-Oct-2009 4 22-Apr-2010 5 Changes Updated Table 19: General operating Updated name of Figure 19: Typical HSI accuracy at VDD = temperatures. Updated Table 43: SPI characteristics Added max values to ...

  • Page 112

    Revision history Date Revision 09-Sep-2010 6 112/113 STM8S103K3 STM8S103F3 STM8S103F2 Changes Updated maximum power dissipation in operating conditions. Updated Θ in Table 57: Thermal JA Replaced package pitch digit by VFQFPN/UFQFPN package digit in Figure 52: STM8S103x access line ordering ...

  • Page 113

    ... ST and the ST logo are trademarks or registered trademarks various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel ...