ST7FLIT15BY0B6 STMicroelectronics, ST7FLIT15BY0B6 Datasheet - Page 87

• Manufacturer Part Number: ST7FLIT15BY0B6
• Description: IC MCU 8BIT 2K FLASH 16-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLIT15BY0B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Processor Series: ST7FLIT1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-8427 - BOARD DEMO USB LI-ION ST7260E2497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 55. Generic SS Timing Diagram
Figure 56. Hardware/Software Slave Select Management
– SS internal must be held high continuously
Figure
(if CPHA = 0)
(if CPHA = 1)
MOSI/MISO
Master SS
Slave SS
Slave SS
4).
SS external pin
SSI bit
Byte 1
SSM bit
1
0
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA = 1 (data latched on second clock edge):
If CPHA = 0 (data latched on first clock edge):
– SS internal must be held low during the entire
– SS internal must be held low during byte
Byte 2
SS internal
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
0.1.5.3).
3):
ST7LITE1xB
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