ST7FLITE39F2M3TR STMicroelectronics, ST7FLITE39F2M3TR Datasheet - Page 114

• Manufacturer Part Number: ST7FLITE39F2M3TR
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.9 Error due to LIN Synch measurement
The LIN Synch Field is measured over eight bit
times.
This measurement is performed using a counter
clocked by the CPU clock. The edge detections
are performed using the CPU clock cycle.
This leads to a precision of 2 CPU clock cycles for
the measurement which lasts 16*8*LDIV clock cy-
cles.
Consequently, this error (D
2 / (128*LDIV
LDIV
er content, leading to the maximum baud rate, tak-
ing into account the maximum deviation of +/-15%.
11.5.9.10 Error due to Baud Rate Quantization
The baud rate can be adjusted in steps of 1 / (16 *
LDIV). The worst case occurs when the “real”
baud rate is in the middle of the step.
This leads to a quantization error (D
to 1 / (2*16*LDIV
11.5.9.11
Maximum Baud Rate
The choice of the nominal baud rate (LDIV
will influence both the quantization error (D
and the measurement error (D
case occurs for LDIV
114/173
MIN
corresponds to the minimum LIN prescal-
Impact
MIN
).
MIN
).
MIN
of
.
Clock
MEAS
MEAS
) is equal to:
Deviation
QUANT
). The worst
) equal
QUANT
NOM
on
)
)
Consequently, at a given CPU frequency, the
maximum possible nominal baud rate (LPR
should be chosen with respect to the maximum tol-
erated deviation given by the equation:
D
+ D
Example:
A nominal baud rate of 20Kbits/s at T
(8 MHz) leads to LDIV
LDIV
D
D
LIN Slave systems
For LIN Slave systems (the LINE and LSLV bits
are set), receivers wake up by LIN Synch Break or
LIN Identifier detection (depending on the LHDM
bit).
Hot Plugging Feature for LIN Slave Nodes
In LIN Slave Mute Mode (the LINE, LSLV and
RWU bits are set) it is possible to hot plug to a net-
work during an ongoing communication flow. In
this case the SCI monitors the bus on the RDI line
until 11 consecutive dominant bits have been de-
tected and discards all the other bits received.
TRA
MEAS
QUANT
REC
MIN
+ 2 / (128*LDIV
= 2 / (128*LDIV
+ D
= 1 / (2*16*LDIV
= 25 - 0.15*25 = 21.25
TCL
< 3.75%
MIN
NOM
MIN
) + 1 / (2*16*LDIV
MIN
) * 100 = 0.00073%
= 25d.
) * 100 = 0.0015%
CPU
= 125ns
MIN
)
MIN
)