ST7FLITE39F2M3TR STMicroelectronics, ST7FLITE39F2M3TR Datasheet - Page 172

• Manufacturer Part Number: ST7FLITE39F2M3TR
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE3xF2
172/173
16-Nov-2007
10-May-07
07-Nov-06
7
8
9
Removed note “negative injection not allowed on PB0 and PB1 pins”
section 13.2.2 on page
Added QFN20 package pinout (with new QFN20 mechanical data):
Figure 105 on page 159
Modified
Modified option list on
Added note 1 to
Added caution “negative injection not allowed on PB0 and PB1 pins”
section 13.2.2 on page
Modified
Modified EOC bit description in
Added caution to
Modified note 1 in
Modified LTCSR1 reset value in
Modified part numbers for QFN20 package in
page 164
Modified
Title of the document changed
Modified
Soldering information section removed
Modified “PACKAGE MECHANICAL DATA” on page 159 (values in inches are rounded to 4
decimal digits instead of 3 decimal digits)
Modified
Modified “DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE”
on page 163 and option list on
section 15.3 on page 165
section 11.6.3.3 on page 122
section 15.1 on page 161
section 7.6.4 on page 34
section 13.7 on page 146
Table 2 on page 7
section 7.5.1 on page 27
section 7.1 on page 23
page 164
132)
132)
page 164
section 11.6.6 on page 123
section 11.3.6 on page 75
(added note to OSCRANGE option bits)
(removed references to DLU)
and added
Table 26 on page 163
section 11.6.3.4 on page 122
Figure 2 on page 6
(Table 2 on page 7
(Table 2 on page 7
and in option list on
and
and
and