ST72F63BK2U1TR STMicroelectronics, ST72F63BK2U1TR Datasheet - Page 115

• Manufacturer Part Number: ST72F63BK2U1TR
• Description: IC MCU 8BIT 8K FLASH 40-QFN
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BK2U1TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-QFN
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 8 Channel / 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7263Bxx
Figure 48. Transfer sequencing
1. Legend:
EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR
register.
EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR
register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared
by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).
Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.
EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.
EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR
register.
EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR
register.
Table 37.
Table 38.
Table 39.
Table 40.
S
S
S
S
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.
Addres
EV
EV
Addres
5
5
s
s
Addres
Addres
s
s
A
A
Slave receiver
Slave Transmitter
Master receiver
Master Transmitter
EV
1
A
EV
A
1
EV
EV
3
6
EV
6
Data1
Data1
EV
8
Data1
Data1
Doc ID 7516 Rev 8
A
A
A
EV
EV
2
3
A
EV
7
Data2
Data2
EV
8
Data2
Data2
A
A
EV
A
3
EV
2
A
EV
.....
7
EV
8
.....
.....
DataN
.....
DataN
DataN
DataN
N
A
On-chip peripherals
A
EV3
-1
N
A
A
EV
2
EV
P
EV
7
8
P
EV
4
P
P
115/186
EV
4