ST7FLITE35F2M6 STMicroelectronics, ST7FLITE35F2M6 Datasheet - Page 24

• Manufacturer Part Number: ST7FLITE35F2M6
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE35F2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5085 - EVAL BOARD UNIV MOTOR CONTROL497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7LITE3xF2
If both the RC oscillator and the PLL are disabled,
f
Figure 12. PLL Output Frequency Timing
Diagram
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC
a stabilization time of t
13.3.4Internal RC Oscillator and
Refer to
of the LOCKED bit in the SICSR register.
24/173
1
OSC
4/8 x
input
freq.
is driven by the external clock.
t
STARTUP
section 7.6.4 on page 34
t
LOCK
STARTUP
STAB
LOCKED bit set
(see
t
PLL
.
STAB
PLL)
) is reached after
for a description
Figure 12
t
and
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
0: MCO clock disabled, I/O port free for general
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
clock f
0: Normal mode (f
1: Slow mode (f
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the
SICSR register. Refer to
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
CR9
purpose I/O.
7
0
7
OSC
CR8
0
or f
CR7
OSC
0
CPU =
/32.
CPU =
CR6
0
f
OSC
f
OSC
section 7.6.4 on page 34
/32)
CR5
0
CR4
0
MCO
CR3
CR2
SMS
0
0