Z8F3221PM020SG Zilog, Z8F3221PM020SG Datasheet - Page 143

• Manufacturer Part Number: Z8F3221PM020SG
• Description: IC ENCORE MCU FLASH 32K 40DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F3221PM020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.620", 15.75mm)
• Processor Series: Z8F322x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4257; Z8F3221PM020SG

PS019918-1206
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
Transfer Format PHASE Equals Zero
Figure 25
0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set
to one. The diagram may be interpreted as either a Master or Slave timing diagram
because the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are
directly connected between the Master and the Slave.
Transfer Format PHASE Equals One
Figure 26
is one. Two waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for
CLKPOL set to 1.
MOSI
MISO
SCK
SCK
SS
illustrates the timing diagram for an SPI transfer in which PHASE is cleared to
on page 131 illustrates the timing diagram for an SPI transfer in which PHASE
Bit7
Bit7
Figure 25. SPI Timing When PHASE is 0
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Z8 Encore!
Bit1
Bit1
Serial Peripheral Interface
Product Specification
Bit0
Bit0
®
64K Series
130