Z8F3221PM020SG Zilog, Z8F3221PM020SG Datasheet - Page 88

• Manufacturer Part Number: Z8F3221PM020SG
• Description: IC ENCORE MCU FLASH 32K 40DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F3221PM020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.620", 15.75mm)
• Processor Series: Z8F322x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4257; Z8F3221PM020SG

Table 36. Interrupt Edge Select Register (IRQES)
Table 37. Interrupt Port Select Register (IRQPS)
PS019918-1206
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
Interrupt Edge Select Register
Interrupt Port Select Register
PAD7S
IES7
7
7
C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
The Interrupt Edge Select (IRQES) register (see
is generated for the rising edge or falling edge on the selected GPIO Port input pin. The
Interrupt Port Select register selects between Port A and Port D for the individual inter-
rupts.
IESx—Interrupt Edge Select x
The minimum pulse width should be greater than 1 system clock to guarantee capture of
the edge triggered interrupt. Shorter pulses may be captured but not guaranteed.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
where x indicates the specific GPIO Port pin number (0 through 7).
The Port Select (IRQPS) register (see
PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as
interrupts. The Interrupt Edge Select register controls the active interrupt edge.
PAD6S
IES6
6
6
PAD5S
IES5
5
5
PAD4S
IES4
4
4
Table
FCDH
FCEH
R/W
R/W
0
0
37) determines the port pin that generates the
PAD3S
IES3
3
3
Table
36) determines whether an interrupt
PAD2S
IES2
2
2
Z8 Encore!
Product Specification
PAD1S
IES1
Interrupt Controller
1
1
®
64K Series
PAD0S
IES0
0
0
75