MC908JK3EMDWER Freescale Semiconductor, MC908JK3EMDWER Datasheet - Page 124

• Manufacturer Part Number: MC908JK3EMDWER
• Description: MCU 8BIT 128RAM 4K FLASH 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JK3EMDWER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: HC08JK
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
262,128 or 8176 2OSCOUT cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. With a 262,128 2OSCOUT cycle overflow option, a 8MHz crystal gives a COP
timeout period of 32.766 ms. Writing any value to location $FFFF before an overflow occurs prevents a
COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter.
A COP reset pulls the RST pin low for 32 × 2OSCOUT cycles and sets the COP bit in the reset status
register (RSR). (See
13.3 I/O Signals
The following paragraphs describe the signals shown in
13.3.1 2OSCOUT
2OSCOUT is the oscillator output signal. 2OSCOUT frequency is equal to the crystal frequency or the
RC-oscillator frequency.
13.3.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see
counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
13.3.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × 2OSCOUT cycles after
power-up.
13.3.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
13.3.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the SIM counter.
13.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG).
(See
124
Chapter 3 Configuration Registers
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
5.7.2 Reset Status Register
MC68HC908JL3E Family Data Sheet, Rev. 4
(CONFIG).)
NOTE
NOTE
(RSR).).
Figure
13.4 COP Control
13-1.
Register) clears the COP
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