MC9S12XET256MAA Freescale Semiconductor, MC9S12XET256MAA Datasheet - Page 760

• Manufacturer Part Number: MC9S12XET256MAA
• Description: MCU 16BIT 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 25
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Package: 80PQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)
20.5.2.2
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1
(SCICR1).
20.5.2.3
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not
affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from
where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset
aborts any transmission or reception in progress and resets the SCI.
The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input
can be used to bring the CPU out of stop mode.
20.5.3
This section describes the interrupt originated by the SCI block.The MCU must service the interrupt
requests.
760
RXEDGIF SCIASR1[7]
Interrupt
BERRIF
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
BKDIF
TDRE
RDRF
IDLE
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
OR
TC
If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.
If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
Table 20-20
SCIASR1[1]
SCIASR1[0]
SCISR1[7]
SCISR1[6]
SCISR1[5]
SCISR1[3]
SCISR1[4]
Interrupt Operation
Source
Wait Mode
Stop Mode
lists the eight interrupt sources of the SCI.
Local Enable
RXEDGIE
BERRIE
BRKDIE
TCIE
ILIE
RIE
TIE
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 20-20. SCI Interrupt Sources
Active high level. Indicates that a byte was transferred from SCIDRH/L to the
transmit shift register.
Active high level. Indicates that a transmit is complete.
Active high level. The RDRF interrupt indicates that received data is available
in the SCI data register.
Active high level. This interrupt indicates that an overrun condition has occurred.
Active high level. Indicates that receiver input has become idle.
Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for
RXPOL = 1) was detected.
Active high level. Indicates that a mismatch between transmitted and received data
in a single wire application has happened.
Active high level. Indicates that a break character has been received.
Description
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