MC9S12XET256MAL Freescale Semiconductor, MC9S12XET256MAL Datasheet - Page 1044

• Manufacturer Part Number: MC9S12XET256MAL
• Description: MCU 16BIT 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 16KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• On-chip Adc: 16-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
27.3.2.12 EEE Tag Counter Register (ETAG)
The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need
to be programmed into the D-Flash EEE partition. The ETAG register is decremented prior to the related
tagged word being programmed into the D-Flash EEE partition. All tagged words have been programmed
into the D-Flash EEE partition once all bits in the ETAG register read 0 and the MGBUSY flag in the
FSTAT register reads 0.
All ETAG bits are readable but not writable and are cleared by the Memory Controller.
27.3.2.13 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see
1044
Offset Module Base + 0x000C
Offset Module Base + 0x000D
Reset
Reset
W
W
R
R
0
0
7
7
CCOBIX[2:0]
= Unimplemented or Reserved
= Unimplemented or Reserved
011
100
101
Table 27-26. FCCOB - NVM Command Mode (Typical Usage)
Figure 27-19. EEE Tag Counter Low Register (ETAGLO)
Figure 27-18. EEE Tag Counter High Register (ETAGHI)
0
0
6
6
Section
MC9S12XE-Family Reference Manual , Rev. 1.23
Byte
LO
LO
LO
HI
HI
HI
0
0
5
5
27.3.2.4). Once ECC fault information has been stored, no other
FCCOB Parameter Fields (NVM Command Mode)
0
0
4
4
ETAG[15:8]
ETAG[7:0]
Data 1 [15:8]
Data 2 [15:8]
Data 3 [15:8]
Data 1 [7:0]
Data 2 [7:0]
Data 3 [7:0]
0
0
3
3
0
0
2
2
Freescale Semiconductor
0
0
1
1
0
0
0
0