MC56F8346VFVER2 Freescale Semiconductor, MC56F8346VFVER2 Datasheet - Page 176

• Manufacturer Part Number: MC56F8346VFVER2
• Description: IC HYBRID CTRLR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVER2

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3 Power Distribution and I/O Ring Implementation
Figure 12-1
contains two internal power regulators. One of them is powered from the V
be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator
is powered from the V
peripherals and the internal memories. This regulator can be turned off, if an external V
is externally applied to the V
In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is
enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.
Notes:
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Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
pins are less than 0.5 inch per capacitor lead
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V
Bypass the V
capacitor such as a tantalum capacitor
Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V
Take special care to minimize noise levels on the V
Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. Designs that do not require debugging functionality, such as
consumer products, should tie these pins together.
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an
interface to this port to allow in-circuit Flash programming
Flash, RAM and internal logic are powered from the core regulator output
V
All circuitry, analog and digital, shares a common V
PP
1 and V
illustrates the general power control incorporated in the 56F8346/56F8146. This chip
DD
and V
PP
DD
2 are not connected in the customer system
and V
DD_IO
SS
circuits.
SS
CAP
pins and provides power to all of the internal digital logic of the core, all
layers of the PCB with approximately 100 μF, preferably with a high-grade
pins.
56F8346 Technical Data, Rev. 15
REF
SS
, V
bus
DDA
and V
SSA
pins
DDA_OSC_PLL
DD
Freescale Semiconductor
and V
DD
DD_CORE
SS
pin and cannot
and V
Preliminary
SS
voltage
(GND)