MC56F8346VFVER2 Freescale Semiconductor, MC56F8346VFVER2 Datasheet - Page 95
MC56F8346VFVER2
Manufacturer Part Number
MC56F8346VFVER2
Description
IC HYBRID CTRLR 16BIT 144-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet
1.MC56F8346VFVE.pdf
(178 pages)
Specifications of MC56F8346VFVER2
Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
62
Program Memory Size
136KB (68K x 16)
Program Memory Type
FLASH
Ram Size
6K x 16
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
For Use With
MC56F8367EVME - EVAL BOARD FOR MC56F83X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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5.6.7.4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.7.5
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.7.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.7.7
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.7.8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
Freescale Semiconductor
Preliminary
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11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ
Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)—Bits 9–8
Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)—Bits 7–6
Reserved—Bits 5–4
IPL)—Bits 3–2
Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0
56F8346 Technical Data, Rev. 15
Register Descriptions
95
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