MC56F8346VFVER2 Freescale Semiconductor, MC56F8346VFVER2 Datasheet - Page 45

• Manufacturer Part Number: MC56F8346VFVER2
• Description: IC HYBRID CTRLR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVER2

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

in the 56F8346/56F8146).
The EMI_MODE pin also affects the reset vector address, as provided in
be configured as address or chip select signals to access addresses at P:$10 0000 and above.
Note: Program RAM is NOT available on the 56F8146 device.
4.3 Interrupt Vector Table
Table 4-5
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
Freescale Semiconductor
Preliminary
1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features, Part 7.
2. This mode provides maximum compatibility with 56F80x parts while operating externally.
3. “EMI_MODE =0” when EMI_MODE pin is tied to ground at boot up.
4. “EMI_MODE =1” when EMI_MODE pin is tied to V
5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip se-
6. Booting from this external address allows prototyping of the internal Boot Flash.
7. The internal Program Flash is relocated in this mode making it accessible.
P:$1F FFFF
P:$10 0000
P:$0F FFFF
P:$03 0000
P:$02 FFFF
P:$02 F800
P:$02 F7FF
P:$02 1000
P:$02 0FFF
P:$02 0000
P:$01 FFFF
P:$01 0000
P:$00 FFFF
P:$00 0000
lects) pins must be reconfigured before this external memory is accessible.
Begin/End
Address
provides the reset and interrupt priority structure, including on-chip peripherals. The table is
External Program Memory
Boot Flash
8KB
COP Reset Address = 02 0002
Boot Location = 02 0000
External Program RAM
Internal Program Flash
128KB
16-Bit External Address Bus
Mode 0 (MA = 0)
Internal Boot
Internal Boot
Table 4-4 Program Memory Map at Reset
On-Chip Program RAM
5
56F8346 Technical Data, Rev. 15
5
Reserved
DD
116KB
4KB
at boot up.
External Program Memory
Boot Flash
8KB
(Not Used for Boot in this Mode)
Internal Program Flash
128KB
External Program RAM
COP Reset Address = 00 0002
Boot Location = 00 0000
16-Bit External Address Bus
EMI_MODE = 0
7
2
,
Mode 1
3
5
External Boot
Table
1
(MA = 1)
External Program Memory
External Program RAM
COP Reset Address = 02 0002
Boot Location = 02 0000
20-Bit External Address Bus
4-4. Additional pins must
EMI_MODE = 1
Interrupt Vector Table
4
6
5
6
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