MC9S12XDT256MAA Freescale Semiconductor, MC9S12XDT256MAA Datasheet - Page 83

• Manufacturer Part Number: MC9S12XDT256MAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 16KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.3.1
Table 2-1
Freescale Semiconductor
gives an overview on all CRG registers.
Module Memory Map
1
2
3
CTFLG is intended for factory test purposes only.
FORBYP is intended for factory test purposes only.
CTCTL is intended for factory test purposes only.
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address
Offset
0x_0A
0x_0B
0x_00
0x_01
0x_02
0x_03
0x_04
0x_05
0x_06
0x_07
0x_08
0x_09
CRG Force and Bypass Test Register (FORBYP)
CRG Reference Divider Register (REFDV)
CRG Interrupt Enable Register (CRGINT)
CRG COP Arm/Timer Reset (ARMCOP)
CRG COP Control Register (COPCTL)
CRG Clock Select Register (CLKSEL)
CRG Test Control Register (CTCTL)
CRG PLL Control Register (PLLCTL)
CRG RTI Control Register (RTICTL)
CRG Test Flags Register (CTFLG)
CRG Synthesizer Register (SYNR)
CRG Flags Register (CRGFLG)
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 2-1. CRG Memory Map
Use
NOTE
1
3
Chapter 2 Clocks and Reset Generator (S12CRGV6)
2
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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