UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 809

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
CHAPTER 5 CLOCK GENERATOR
p.212
p.212
p.230
p.231
p.235
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
p.255
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
pp.318, 324,
325
p.324
p.325
CHAPTER 8 8-BIT TIMERS H0 AND H1
p.339
pp.344, 345
p.345
CHAPTER 10 REAL-TIME COUNTER
p.373
CHAPTER 12 A/D CONVERTER
p.402
p.403
p.412
p.413
pp.413 to 415 Change of Figure 12-9. Format of A/D Port Configuration Registers 0, 1 (ADPC0, ADPC1)
p.415
p.416
p.417
p.420
Remark “Classification” in the above table classifies revisions as follows.
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d):
Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Change of description of (9) Peripheral enable register 0 (PER0) in 5.3 Registers Controlling Clock
Generator
Change of Figure 5-12. Format of Peripheral Enable Register 0 (PER0)
Addition of Note to Figure 5-18. CPU Clock Status Transition Diagram (When LVI Default Start
Mode Function Stopped Is Set (Option Byte: LVISTART = 0), 78K0/KY2-L, 78K0/KA2-L, and
78K0/KB2-L)
Addition of Note to Figure 5-19. CPU Clock Status Transition Diagram (When LVI Default Start
Mode Function Stopped Is Set (Option Byte: LVISTART = 0), 78K0/KC2-L)
Addition of Note to (11) • STOP mode (H) set while CPU is operating with internal high-speed
oscillation clock (B) • STOP mode (I) set while CPU is operating with high-speed system clock
(C) in Table 5-6. CPU Clock Transition and SFR Register Setting Examples (4/4)
Addition of (5) Port alternate switch control register (MUXSEL) (78K0/KA2-L (25-pin and 32-pin
products) only) to 6.3 Registers Controlling 16-Bit Timer/Event Counter 00
Addition of MUXSEL and PM0 to 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
Change of (3) Port alternate switch control register (MUXSEL) (78K0/KA2-L (25-pin) only) and (4)
Port mode registers 0, 1, 3 (PM0, PM1, PM3) of 7.3 Registers Controlling 8-Bit Timer/Event
Counters 50 and 51
Addition of Figure 7-12. Format of Port Mode Register 0 (PM0)
Addition of name of registers to 8.3 Registers Controlling 8-Bit Timers H0 and H1
Change of (3) Port alternate switch control register (MUXSEL) (78K0/KA2-L (25, 32-pin products)
only) and (4) Port mode register 0 (PM0), port mode register 1 (PM1), port mode register 3 (PM3)
of 8.3 Registers Controlling 8-Bit Timers H0 and H1
Addition of Figure 8-9. Format of Port Mode Register 0 (PM0)
Change of (1) Peripheral enable register 0 (PER0) of 10.3 Registers Controlling Real-Time
Counter
Change of Figure 12-1. Block Diagram of A/D Converter
Change of (4) PGAOUT signal (products with operational amplifier only) in 12.2 Configuration of
A/D Converter
Change of Figure 12-8. Format of Analog Input Channel Specification Register (ADS)
Change of (6) A/D port configuration registers 0, 1 (ADPC0, ADPC1) in 12.2 Configuration of A/D
Converter
Change of (7) Port mode registers 1, 2, 7 (PM1, PM2, PM7) in 12.2 Configuration of A/D Converter
Change of Figure 12-11. Format of Port Mode Register 2 (PM2)
Addition of Figure 12-12. Format of Port Mode Register 7 (PM7) (78K0/KA2-L (32-pin products))
Change of Table 12-6. Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin
Description
APPENDIX C REVISION HISTORY
Classification
(d)
(d)
(d)
(d)
(d)
(d)
(d)
(d)
(d)
(d)
(d)
(d)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(2/4)
795