UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 237

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
5.6.2 Example of controlling internal high-speed oscillation clock
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The following describes examples of clock setting procedures for the following cases.
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clock
(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
speed system clock as peripheral hardware clock
<1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register)
<2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM register)
Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal
<1> Confirming the CPU clock status (PCC and MCM registers)
• 78K0/KY2-L, 78K0/KA2-L, and 78K0/KB2-L
• 78K0/KC2-L
<2> Stopping the high-speed system clock (MOC register)
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating.
Wait until RSTS is set to 1
2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral
MCS
CLS
0
1
0
0
1
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU
clock to a clock other than the high-speed system clock.
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
high-speed oscillation clock is selected as the CPU clock.
hardware clock.
peripheral hardware that is operating on the high-speed system clock.
Internal high-speed oscillation clock
High-speed system clock
MCS
0
1
×
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
Note 2
.
CPU Clock Status
CPU Clock Status
CHAPTER 5 CLOCK GENERATOR
Note 1
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