UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 606

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Maskable
Interrupt
Type
Notes 1.
Internal
External
Internal
External
Internal
Internal/
External
2.
3.
4.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon the
timing when the INTTM5H1 signal is generated (refer to Figure 8-14 Transfer Timing).
Configuration
Type
Basic
(A)
(B)
(A)
(B)
(A)
Note 1
Priority
Default
10
11
12
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
Note 2
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTSRE6
INTSR6
INTST6
INTCSI10 End of CSI10 communication
INTCSI11 End of CSI11 communication
INTTMH1 Match between TMH1 and CMP01
INTTMH0 Match between TMH0 and CMP00
INTTM50
INTTM000 Match between TM00 and CR000
INTTM010 Match between TM00 and CR010
INTAD
INTP6
INTRTCI
INTTM51
Note 4
Table 17-1. Interrupt Source List (1/2)
Name
Low-voltage detection
Pin input edge detection
UART6 reception error generation
End of UART6 reception
End of UART6 transmission
(when compare register is specified)
(when compare register is specified)
Match between TM50 and CR50
(when compare register is specified)
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
(when compare register is specified),
TI000 pin valid edge detection
(when capture register is specified)
End of A/D conversion
Pin input edge detection
Interval signal detection of real-time
counter
Match between TM51 and CR51
(when compare register is specified)
Interrupt Source
Trigger
Note 3
CHAPTER 17 INTERRUPT FUNCTIONS
Address
000AH
000CH
000EH
001AH
001CH
001EH
002AH
0004H
0006H
0008H
0010H
0012H
0014H
0016H
0018H
0018H
0020H
0022H
0024H
0026H
0028H
Vector
Table
KY
2-L
pin
16
s
√
√
√
−
−
−
−
√
√
√
−
−
√
−
−
√
√
√
−
−
√
pin
20
KA2-L
√
√
√
√
√
−
−
√
√
√
−
−
√
−
−
√
√
√
−
−
√
s
25,
pin
32
s
√
√
−
√
√
√
√
√
√
√
−
√
√
−
−
√
√
√
−
−
√
2-L
KB
pin
30
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
−
−
√
s
40p
ins
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
−
√
√
KC2-L
pin
44
s
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
−
√
√
592
pin
48
s
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√