UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 744

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Bit
manipulate
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
AND1
OR1
XOR1
SET1
CLR1
SET1
CLR1
NOT1
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
register (PCC).
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW. bit
CY, [HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Operands
Bytes
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
2
3
2
2
2
2
3
2
2
2
1
1
1
Note 1
6
−
4
−
6
6
−
4
−
6
6
−
4
−
6
4
−
4
−
6
4
−
4
−
6
2
2
2
Clocks
Note 2
7
7
−
7
7
7
7
−
7
7
7
7
−
7
7
6
8
−
6
8
6
8
−
6
8
−
−
−
(saddr.bit) ← 1
(saddr.bit) ← 0
CY ← CY ∧ (saddr.bit)
CY ← CY ∧ sfr.bit
CY ← CY ∧ A.bit
CY ← CY ∧ PSW.bit
CY ← CY ∧ (HL).bit
CY ← CY ∨ (saddr.bit)
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
CY ← CY ∨ (HL).bit
CY ← CY ∨ (saddr.bit)
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
CY ← CY ∨ (HL).bit
sfr.bit ← 1
A.bit ← 1
PSW.bit ← 1
(HL).bit ← 1
sfr.bit ← 0
A.bit ← 0
PSW.bit ← 0
(HL).bit ← 0
CY ← 1
CY ← 0
CY ← CY
CPU
) selected by the processor clock control
CHAPTER 27 INSTRUCTION SET
Operation
Z AC CY
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
0
×
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