PIC18F4539T-E/ML Microchip Technology, PIC18F4539T-E/ML Datasheet
PIC18F4539T-E/ML
Specifications of PIC18F4539T-E/ML
Related parts for PIC18F4539T-E/ML
PIC18F4539T-E/ML Summary of contents
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... Enhanced FLASH Microcontrollers 2002 Microchip Technology Inc. PIC18FXX39 Data Sheet with Single Phase Induction Motor Control Kernel Preliminary DS30485A ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... PIC18F4439 12K 6144 640 PIC18F4539 24K 12288 1408 2002 Microchip Technology Inc. PIC18FXX39 Peripheral Features: • High current sink/source 25 mA/25 mA • Three external interrupt pins • Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler • Timer1 module: 16-bit timer/counter • Timer3 module: 16-bit timer/counter • ...
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... QFN RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VDD RB0/INT0 RB1/INT1 RB2/INT2 DS30485A-page RC0/T13CKI 32 2 OSC2/CLKO/RA6 31 3 OSC1/CLKI 30 4 PIC18F4439 PIC18F4539 RE2/AN7/ RE1/AN6/ RE0/AN5/ RA5/AN4/SS/LVDIN RA4/T0CKI 11 1 OSC2/CLKO/RA6 OSC1/CLKI PIC18F4439 PIC18F4539 7 RE2/AN7/ RE1/AN6/ RE0/AN5/ RA5/AN4/SS/LVDIN RA4/T0CKI Preliminary SS DD 2002 Microchip Technology Inc. ...
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... MCLR/V RA0/AN0 RA1/AN1 RA2/AN2/V REF RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS/LVDIN RE0/AN5/RD RE1/AN6/WR RE2/AN7/ OSC1/CLKI OSC2/CLKO/RA6 RC0/T13CKI PWM2 PWM1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 28-Pin DIP, SOIC MCLR/V RA0/AN0 RA1/AN1 RA2/AN2/V RA3/AN3/V RA4/T0CKI RA5/AN4/SS/LVDIN OSC1/CLKI OSC2/CLKO/RA6 RC0/T13CKI PWM2 PWM1 RC3/SCK/SCL 2002 Microchip Technology Inc ...
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... Appendix B: Device Differences......................................................................................................................................................... 305 Appendix C: Conversion Considerations ........................................................................................................................................... 306 Appendix D: Migration from High-End to Enhanced Devices............................................................................................................. 307 Index .................................................................................................................................................................................................. 309 On-Line Support................................................................................................................................................................................. 317 Systems Information and Upgrade Hot Line ...................................................................................................................................... 317 Reader Response .............................................................................................................................................................................. 318 PIC18FXX39 Product Identification System....................................................................................................................................... 319 DS30485A-page 4 Preliminary 2002 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2002 Microchip Technology Inc. PIC18FXX39 Preliminary DS30485A-page 5 ...
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... PIC18FXX39 NOTES: DS30485A-page 6 Preliminary 2002 Microchip Technology Inc. ...
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... A/D Converter: This module offers conversion channels for flexibility in sensor monitoring and control, as well as the ability to do conversions while the device is in SLEEP mode. 2002 Microchip Technology Inc. PIC18FXX39 1.2 Details on Individual Family Members Devices in the PIC18FXX39 family are available in 28-pin (PIC18F2X39) and 40/44-pin (PIC18F4X39) packages ...
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... POR, BOR, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) Yes Yes Yes Yes 75 Instructions 75 Instructions 40-pin DIP 40-pin DIP 44-pin TQFP 44-pin TQFP 44-pin QFN 44-pin QFN 2002 Microchip Technology Inc. ...
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... The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction). 2: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent. 2002 Microchip Technology Inc. Data Bus<8> Data Latch ...
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... RA6 PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3 RB4 RB5/PGM RB6/PGC RB7/PGD PORTC RC0/T13CKI RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD0/PSP0 RD1/PSP1 8 RD2/PSP2 RD3/PSP3 8 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS PWM1 PWM2 A/D Converter Data EEPROM 2002 Microchip Technology Inc. ...
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... SS LVDIN RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V 2002 Microchip Technology Inc. Pin Buffer Type Master Clear (input) or high voltage ICSP programming enable pin Master Clear (Reset) input. This pin is an active low RESET to the device ...
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... TTL Digital I/O. Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description 2002 Microchip Technology Inc. ...
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... PWM2 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V 2002 Microchip Technology Inc. Pin Buffer Type PORTC is a bi-directional I/O port. I/O ST Digital I/ Timer1/Timer3 external clock input. I/O ST Digital I/O. I/O ST Synchronous serial clock input/output for SPI mode ...
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... Digital I/O. Open drain when configured as output Timer0 external clock input. 24 I/O TTL Digital I/O. I Analog Analog input SPI Slave Select input. I Analog Low Voltage Detect input. (See the OSC2/CLKO/RA6 pin.) CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description 2002 Microchip Technology Inc. ...
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... PGD Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V 2002 Microchip Technology Inc. Pin Buffer Type Type PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... USART Synchronous Clock (see related RX/DT). 1 I/O ST Digital I/ USART Asynchronous Receive. I/O ST USART Synchronous Data (see related TX/CK — PWM Channel 1 (motor control) output — PWM Channel 2 (motor control) output. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description 2002 Microchip Technology Inc. ...
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... PSP7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V 2002 Microchip Technology Inc. Pin Buffer Type Type PORTD is a bi-directional I/O port Parallel Slave Port (PSP) for interfacing to a microprocessor port. ...
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... Positive supply for logic and I/O pins. — P — Ground reference for analog modules. — P — Positive supply for analog modules. — — These pins should be left unconnected. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description 2002 Microchip Technology Inc. ...
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... Figure 2-1 shows connections. The PIC18FXX39 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. 2002 Microchip Technology Inc. FIGURE 2-1: (1) C1 XTAL S (2) R (1) C2 Note 1: See Table 2-1 for recommended values of C1 and C2 ...
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... A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out that is called T Preliminary EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1 PIC18FXX39 /4 OSC2 EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1 PIC18FXX39 I/O (OSC2) . PLL 2002 Microchip Technology Inc. ...
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... OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin ECIO EC HS Feedback inverter disabled, at quiescent voltage level Note: See Table 3-1 in the “Reset” section, for time-outs due to SLEEP and MCLR Reset. 2002 Microchip Technology Inc. Phase Comparator F IN Loop Filter F OUT ÷ ...
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... PIC18FXX39 NOTES: DS30485A-page 22 Preliminary 2002 Microchip Technology Inc. ...
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... Ripple Counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. 2002 Microchip Technology Inc. PIC18FXX39 Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... Special Function Registers, while Table 3-3 shows the RESET conditions for all the registers. Preliminary falls below parameter D005 for greater falls below DD rises above DD rises above then will keep DD DD drops below BV while the DD DD rises above BV , the Power-up Timer DD 2002 Microchip Technology Inc. ...
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... Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2002 Microchip Technology Inc. (2) Power-up PWRTE = 1 1024 T ...
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... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (3) uuuu uuuu (3) uuuu -u-u (3) uu-u u-uu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A 2002 Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’. 2002 Microchip Technology Inc. MCLR Resets Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’. 2002 Microchip Technology Inc. MCLR Resets Power-on Reset, ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30485A-page 30 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary 2002 Microchip Technology Inc CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL 2002 Microchip Technology Inc PWRT T OST T PWRT T OST T PLL ...
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... PIC18FXX39 NOTES: DS30485A-page 32 Preliminary 2002 Microchip Technology Inc. ...
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... Note: Size of memory areas not to scale. 2002 Microchip Technology Inc. The PIC18F2539 and PIC18F4539 each have a total of 24 Kbytes, or 12K of single word instructions of FLASH memory, from addresses 0000h to 5FFFh. The next 8 Kbytes beyond this space (from 6000h to 7FFFh) are reserved for the Motor Control kernel ...
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... POR occurs. Note: Returning a value of zero to the underflow has the effect of vectoring the program to the RESET vector, where the stack conditions can be verified and appropriate actions can be taken. stack Preliminary System for return stack 2002 Microchip Technology Inc. ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 2002 Microchip Technology Inc. PIC18FXX39 U-0 R/W-0 R/W-0 R/W-0 — ...
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... Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4- PC+2 Execute INST (PC) Fetch INST (PC+2) Preliminary GOTO and program branch Internal Phase Clock PC+4 Execute INST (PC+2) Fetch INST (PC+4) 2002 Microchip Technology Inc. ...
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... MOVLW Instruction 2: GOTO Instruction 3: MOVFF 2002 Microchip Technology Inc. A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles ...
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... Data is transferred to/from program memory, one byte at a time. A description of the Table Read/Table Write operation is shown in Section 5.1. Preliminary 2002 Microchip Technology Inc. ...
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... GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 4.10 provides a detailed description of the Access RAM. 2002 Microchip Technology Inc. PIC18FXX39 4.9.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indi- rectly ...
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... Access RAM High (SFRs) FFh When the BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). 2002 Microchip Technology Inc. ...
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... Bank 6 to • Bank 14 = 1110 00h = 1111 Bank 15 FFh When the BSR is used to specify the RAM location that the instruction uses. 2002 Microchip Technology Inc. Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh 200h GPR ...
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... F91h — F90h — F8Fh — F8Eh — (2) F8Dh LATE (2) F8Ch LATD (4) F8Bh LATC F8Ah LATB F89h LATA F88h — F87h — F86h — F85h — (2) F84h PORTE (2) F83h PORTD (4) F82h PORTC F81h PORTB F80h PORTA 2002 Microchip Technology Inc. ...
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... RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear. 2002 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 — ...
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... TMR3CS TMR3ON 0000 0000 28, 109 28, 168 0000 0000 0000 0000 28, 175, 178 0000 0000 28, 173, 176 TRMT TX9D 28, 166 0000 -010 OERR RX9D 28, 167 0000 000x 28, 61, 0000 0000 65 28, 65 0000 0000 28, 61, ---- ---- 28, 62 xx-0 x000 2002 Microchip Technology Inc. ...
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... RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear. 2002 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 — ...
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... Section 4.12 provides a description of indirect address- ing, which allows linear addressing of the entire RAM space. Direct Addressing (3) From Opcode 0 (3) 00h 01h 000h 100h Data (1) Memory 0FFh 1FFh Bank 0 Bank 1 Preliminary 0Eh 0Fh E00h F00h EFFh FFFh Bank 14 Bank 15 2002 Microchip Technology Inc. ...
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... FSR register being the address of the data instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads 2002 Microchip Technology Inc. PIC18FXX39 the data from the FSR1H:FSR1L ...
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... INDIRECT ADDRESSING 11 Location Select Note 1: For register file map detail, see Table 4-1. DS30485A-page 48 0h RAM Address FFFh 12 File Address = Access of an Indirect Addressing Register File FSR Indirect Addressing FSR Register 0 0000h Data (1) Memory 0FFFh Preliminary 2002 Microchip Technology Inc. ...
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... Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). ...
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... Power-on Resets may be detected. U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2002 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2002 Microchip Technology Inc. PIC18FXX39 5.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. Preliminary 2002 Microchip Technology Inc. Table Latch (8-bit) TABLAT ...
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... Initiates an EEPROM read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Does not initiate an EEPROM read Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC18FXX39 U-0 R/W-0 R/W-x R/W-0 — ...
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... Figure 5-3 describes the relevant boundaries of TBLPTR based operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 WRITE - TBLPTR<21:3> READ - TBLPTR<21:0> Preliminary on FLASH program memory TBLPTRL 0 2002 Microchip Technology Inc. ...
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... MOVF TABLAT, W MOVWF WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD 2002 Microchip Technology Inc. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation. The internal program memory is typically organized by words ...
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... TBLPTR with the base ; address of the memory block ; point to FLASH program memory ; access FLASH program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary 2002 Microchip Technology Inc. ...
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... WREN to enable byte writes. 8. Disable interrupts. 9. Write 55h to EECON2. 2002 Microchip Technology Inc. operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. ...
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... TBLWT holding register. ; loop until buffers are full Preliminary 2002 Microchip Technology Inc. ...
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... PIE2 — — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used during FLASH/EEPROM access. 2002 Microchip Technology Inc. ; point to FLASH program memory ; access FLASH program memory ; enable write to memory ; disable interrupts ; write 55h ; write AAh ...
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... PIC18FXX39 NOTES: DS30485A-page 60 Preliminary 2002 Microchip Technology Inc. ...
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... The write time will vary with voltage and temperature, as well as from chip to chip. Please refer to parameter D122 (Electrical Characteristics, Section 23.0) for exact limits. 2002 Microchip Technology Inc. 6.1 EEADR The address register can address maximum of 256 bytes of data EEPROM. ...
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... Does not initiate an EEPROM read Legend Readable bit - n = Value at POR DS30485A-page 62 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2002 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
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... INTCON, GIE . . . BCF EECON1, WREN 2002 Microchip Technology Inc. (EECON1<6>), and (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation) ...
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... Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts Preliminary 2002 Microchip Technology Inc. ...
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... FA1h PIR2 — — FA0h PIE2 — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. 2002 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF — FREE ...
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... PIC18FXX39 NOTES: DS30485A-page 66 Preliminary 2002 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2002 Microchip Technology Inc. PIC18FXX39 7.2 Operation Example 7-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...
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... ARG2H, W SUBWFB RES3 ; CONT_CODE : Preliminary SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ARG1H * ARG2H -> ; PRODH:PRODL ; ARG1L * ARG2H -> ; PRODH:PRODL ; F ; Add cross ; products ARG1H * ARG2L -> ; PRODH:PRODL ; F ; Add cross ; products ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; 2002 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. 2002 Microchip Technology Inc. PIC18FXX39 While PIC18FXX39 devices have two interrupt priority levels like other PIC18 microcontrollers, their allocation is different. In these devices, the high priority interrupt is used exclusively by the ProMPT kernel via the Timer2 match interrupt ...
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... INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary 2002 Microchip Technology Inc. Wake- SLEEP mode Interrupt to CPU Vector to location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEL/PEIE GIE/GIEH ...
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... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit ...
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... DS30485A-page 72 R/W-1 R/W-1 U-0 R/W-1 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-1 (1) — RBIP bit Bit is unknown 2002 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2002 Microchip Technology Inc. U-0 R/W-0 R/W-0 (1) — ...
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... R-0 R-0 R/W-0 U-0 RCIF TXIF SSPIF — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2002 Microchip Technology Inc. R/W-0 R/W-0 (2) TMR2IF TMR1IF bit Bit is unknown ...
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... TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. U-0 U-0 R/W-0 R/W-0 — — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘ ...
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... R = Readable bit - n = Value at POR DS30485A-page 76 R/W-0 R/W-0 R/W-0 U-0 RCIE TXIE SSPIE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 (2) TMR2IE TMR1IE bit Bit is unknown 2002 Microchip Technology Inc. ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 Unimplemented: Read as ‘0’ Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. U-0 U-0 R/W-0 R/W-0 — — EEIE BCLIE W = Writable bit U = Unimplemented bit, read as ‘ ...
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... R/W-1 (2) (2) (2) (2) RCIP TXIP SSPIP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary by the API method void U-1 R/W-1 R/W-1 (3) (2) — TMR2IP TMR1IP bit Bit is unknown 2002 Microchip Technology Inc. ...
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... TMR3IP : TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘1’ Note 1: Maintain this bit cleared (= 0). Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. U-0 U-0 R/W-1 R/W-1 (1) — — EEIP BCLIP W = Writable bit U = Unimplemented bit, read as ‘ ...
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... Legend Readable bit - n = Value at POR DS30485A-page 80 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2002 Microchip Technology Inc. ...
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... BSR MOVF W_TEMP, W MOVFF STATUS_TEMP,STATUS 2002 Microchip Technology Inc. 8.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set flag bit TMR0IF. The interrupt can be enabled or disabled by setting or clearing enable bit TMR0IE (INTCON< ...
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... PIC18FXX39 NOTES: DS30485A-page 82 Preliminary 2002 Microchip Technology Inc. ...
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... The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. 2002 Microchip Technology Inc. EXAMPLE 9-1: CLRF PORTA CLRF LATA ...
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... Bus RD LATA (1) I/O pin N WR LATA or PORTA TRISA RD TRISA ECRA6 or RCRA6 Enable RD PORTA only. Note 1: I/O pins have protection diodes to V Preliminary BLOCK DIAGRAM OF RA6 PIN Data Latch N I/O pin TRIS Latch TTL Input Buffer and 2002 Microchip Technology Inc. (1) ...
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... PORTA Data Direction Register ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by PORTA. 2002 Microchip Technology Inc. Input/output or analog input. Input/output or analog input. Input/output or analog input or V Input/output or analog input Input/output or external clock input for Timer0. ...
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... ICSP mode entry. 2: When using Low Voltage ICSP program- ming (LVP), the pull-up on RB5 becomes disabled. If TRISB bit 5 is cleared, thereby setting RB5 as an output, LATB bit 5 must also be cleared for proper operation. Preliminary 2002 Microchip Technology Inc Weak P Pull-up (1) I/O pin ...
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... Data Bus WR LATB or WR PORTB WR TRISB RD TRISB RD LATB RD PORTB Note 1: I/O pin has diode protection enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>). 2002 Microchip Technology Inc (2) Weak P Pull-up Data Latch D Q I/O pin ...
Page 90
... Value on Value on Bit 0 All Other POR, BOR RESETS RB0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 000x 0000 000u RBIP 1111 -1-1 1111 -1-1 INT1IF 11-0 0-00 11-0 0-00 2002 Microchip Technology Inc. ...
Page 91
... Peripheral Data In Note 1: I/O pins have diode protection Port/Peripheral Select signal selects between port data (input) and peripheral output. 3: Peripheral Output Enable is only active if Peripheral Select is active. 2002 Microchip Technology Inc. EXAMPLE 9-3: CLRF PORTC CLRF LATC MOVLW 0xC9 MOVWF TRISC PIC18FXX39 devices differ from other PIC18 micro- controllers in allocation of PORTC pins ...
Page 92
... Addressable USART Synchronous Data. Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 * * LATC4 LATC3 * * TRISC4 TRISC3 * * Preliminary mode). Value on Value on Bit 0 All Other POR, BOR RESETS RC0 xxxx xxxx uuuu uuuu LATC0 xxxx xxxx uuuu uuuu TRISC0 1111 1111 1111 1111 2002 Microchip Technology Inc. ...
Page 93
... Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2002 Microchip Technology Inc. PIC18FXX39 FIGURE 9-8: PORTD BLOCK DIAGRAM IN I/O PORT MODE RD LATD Data Bus LATD or PORTD ...
Page 94
... RD3 RD2 RD1 PSPMODE — PORTE Data Direction bits Preliminary Function Value on Value on Bit 0 All Other POR, BOR RESETS RD0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 2002 Microchip Technology Inc. ...
Page 95
... MOVWF ADCON1 ; for digital inputs MOVLW 0x05 ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs 2002 Microchip Technology Inc. PIC18FXX39 FIGURE 9-9: PORTE BLOCK DIAGRAM IN I/O PORT MODE RD LATE Data Bus LATE or PORTE CK Data Latch ...
Page 96
... Value at POR DS30485A-page 94 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 TRISE2 TRISE1 TRISE0 bit Bit is unknown 2002 Microchip Technology Inc. ...
Page 97
... IBOV ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PORTE. 2002 Microchip Technology Inc. Function Input/output port pin or analog input or read control input in Parallel Slave Port mode (1) For RD (PSP mode Not a read operation 0 = Read operation ...
Page 98
... TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pin has protection diodes Preliminary PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Q RDx Pin TTL Read RD TTL Chip Select CS TTL Write WR TTL and 2002 Microchip Technology Inc. ...
Page 99
... RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. 2002 Microchip Technology Inc Bit 4 Bit 3 Bit 2 Bit 1 — — RE2 RE1 — ...
Page 100
... PIC18FXX39 NOTES: DS30485A-page 98 Preliminary 2002 Microchip Technology Inc. ...
Page 101
... Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC18FXX39 Figure 10-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 10-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
Page 102
... T0PS2, T0PS1, T0PS0 1 Sync with Internal TMR0L Clocks delay PSA Preliminary Data Bus 8 TMR0L Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2002 Microchip Technology Inc. ...
Page 103
... T0CS TRISA — PORTA Data Direction Register Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 2002 Microchip Technology Inc. 10.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control; it can be changed “on-the-fly” during program execution ...
Page 104
... PIC18FXX39 NOTES: DS30485A-page 102 Preliminary 2002 Microchip Technology Inc. ...
Page 105
... Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. Figure 11 simplified block diagram of the Timer1 module. Register 11-1 details the Timer1 control register, which sets the Operating mode of the Timer1 module. Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON (T1CON< ...
Page 106
... TMR1L 1 TMR1ON On/Off T1SYNC 1 Prescaler OSC Internal 0 Clock 2 T1CKPS1:T1CKPS0 TMR1CS 8 TMR1L TMR1ON on/off T1SYNC 1 Prescaler OSC Internal 0 Clock TMR1CS T1CKPS1:T1CKPS0 Preliminary Synchronized Clock Input Synchronize det SLEEP Input Synchronized 0 Clock Input 1 Synchronize det 2 SLEEP Input 2002 Microchip Technology Inc. ...
Page 107
... Shaded cells are not used by the Timer1 module. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear. 2002 Microchip Technology Inc. the user with the ability to accurately read all 16-bits of ...
Page 108
... PIC18FXX39 NOTES: DS30485A-page 106 Preliminary 2002 Microchip Technology Inc. ...
Page 109
... TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16 (ProMPT Module) 2002 Microchip Technology Inc. PIC18FXX39 Note: In PIC18FXX39 devices, Timer2 is used exclusively as a time-base for the PWM modules in motor control applications. As such not available to users as a resource. Although their locations are ...
Page 110
... PIC18FXX39 NOTES: DS30485A-page 108 Preliminary 2002 Microchip Technology Inc. ...
Page 111
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. Figure 13 simplified block diagram of the Timer3 module. Register 13-1 shows the Timer1 control register, which sets the Operating mode of the Timer1 module. R/W-0 R/W-0 R/W-0 — ...
Page 112
... TMR3L 1 TMR3ON On/Off T3SYNC 1 Prescaler OSC Internal 0 Clock TMR3CS T3CKPS1:T3CKPS0 8 TMR3 TMR3L TMR3ON On/Off OSC Internal 0 Clock T3CKPS1:T3CKPS0 TMR3CS Preliminary Synchronized Clock Input Synchronize det 2 SLEEP Input Synchronized 0 Clock Input 1 T3SYNC Synchronize Prescaler det 2 SLEEP Input 2002 Microchip Technology Inc. ...
Page 113
... T1CKPS1 T1CKPS0 — T3CON RD16 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. 2002 Microchip Technology Inc. (PIR2<1>). This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit, TMR3IE (PIE2<1>). Bit 4 Bit 3 Bit 2 ...
Page 114
... PIC18FXX39 NOTES: DS30485A-page 112 Preliminary 2002 Microchip Technology Inc. ...
Page 115
... Single Phase N AC Input G I/OPorts Digital PIC18FXX39 I/O Interface A/D Analog 2002 Microchip Technology Inc. ratio, the motor’s speed can be varied with constant current. Maintaining this constant ratio is the function of the Motor Control kernel. EQUATION 14- where applied voltage I is motor current φ ...
Page 116
... Input Frequency (Hz) TABLE 14-1: DATA POINTS FOR THE DEFAULT V/F CURVE Frequency (Hz 104 112 120 128 Preliminary 2002 Microchip Technology Inc motor rated should equal f at 100% modulation 60 80 100 120 140 % Modulation 100 110 133 133 133 133 ...
Page 117
... Microchip Technology Inc. Shaded Pole Blower 115V 3.5/3.25A 50/60 Hz 1570 RPM 1/10 HP Measured Deviation (%) Output Voltage (RMS) Linear V/F Curve (Pre-programmed) 1.3 22.8 1.1 28.2 1.0 33.5 1.2 42.0 1 ...
Page 118
... Microchip Technology Inc. ...
Page 119
... Resources used: 1 stack level Range of values 127 Description: Returns the current Boost Frequency in Hz. unsigned char ProMPT_GetBoostStartModulation(void) Resources used: 1 stack level Range of values BoostEndModulation Description: Returns the Start Modulation (in %) used in the Boost logic. 2002 Microchip Technology Inc. PIC18FXX39 Preliminary DS30485A-page 117 ...
Page 120
... When PWMfrequency is ‘0’, the module’s operating frequency is 9.75 kHz. When PWMfrequency is ‘1’, the module’s operating frequency is 19.53 kHz. Note: Since the high priority interrupt is used, the fast call/return cannot be used by other routines. DS30485A-page 118 . This method returns the current TM Preliminary 2002 Microchip Technology Inc. ...
Page 121
... Modulation is determined from the V/F curve, which is set up with the ProMPT_SetVFCurve method. If frequency = 0, the drive will stop. If the drive is stopped and frequency > 0, the drive will start. 2002 Microchip Technology Inc. PIC18FXX39 Preliminary ...
Page 122
... Resources used: 1 stack level Description: The value of the Tick timer flag becomes ‘1’ every 62.5 ms (1/16 second). This can be used for timing applications. clearTick must be called in the timing routine when this is serviced. DS30485A-page 120 Preliminary 2002 Microchip Technology Inc. ...
Page 123
... ProMPT_Tick(void); ProMPT_ClearTick(void ProMPT_Tick(void); ProMPT_ClearTick(void ProMPT_SetFrequency(0); while(1); } 2002 Microchip Technology Inc. FIGURE 14-3: is shown in // Initialize the ProMPT block // Set motor frequency to 10Hz // Set counter for 10 sec @ 1/16 sec per tick // Tick of 1/16 sec // Clearing the Tick flag // Set acceleration rate to 10 Hz/sec ...
Page 124
... PIC18FXX39 NOTES: DS30485A-page 122 Preliminary 2002 Microchip Technology Inc. ...
Page 125
... Comparator Clear Timer, PWM1 pin and PR2 latch Duty Cycle Note 1: 8-bit timer is concatenated with 2-bit internal Q clock bits of the prescaler to create a 10-bit time-base. 2002 Microchip Technology Inc. FIGURE 15-2: Period Duty Cycle TMR2 = PR2 module 15.1.1 PWM PERIOD The PWM period is specified when the Motor Control module is initialized ...
Page 126
... TMR1IP 0000 0000 0000 0000 * * 0000 0000 0000 0000 * * 1111 1111 1111 1111 * * -000 0000 -000 0000 * * xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu * * --00 0000 --00 0000 * * xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu * * --00 0000 --00 0000 2002 Microchip Technology Inc. ...
Page 127
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2002 Microchip Technology Inc. PIC18FXX39 16.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four modes of SPI are supported ...
Page 128
... A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary the SSPBUF is not R-0 R-0 R-0 R bit Bit is unknown 2002 Microchip Technology Inc. ...
Page 129
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved, or implemented mode only. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 ...
Page 130
... Example 16-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF reg- BF ister. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions. Preliminary 2002 Microchip Technology Inc. ...
Page 131
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2002 Microchip Technology Inc. 16.3.4 TYPICAL CONNECTION Figure 16-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock ...
Page 132
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit2 bit5 bit4 bit1 bit3 bit2 bit5 bit4 bit3 bit1 Preliminary ) ) 4 Clock Modes bit0 bit0 bit0 bit0 Next Q4 cycle after Q2↓ 2002 Microchip Technology Inc. ...
Page 133
... SSPIF Interrupt Flag SSPSR to SSPBUF 2002 Microchip Technology Inc. longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON< ...
Page 134
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS30485A-page 132 bit6 bit2 bit5 bit4 bit3 bit6 bit2 bit5 bit4 bit3 Preliminary bit1 bit0 bit0 Next Q4 cycle after Q2↓ bit1 bit0 bit0 Next Q4 cycle after Q2↓ 2002 Microchip Technology Inc. ...
Page 135
... Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. * Reserved bits; do not modify. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear. 2002 Microchip Technology Inc. 16.3.10 BUS MODE COMPATIBILITY ...
Page 136
... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg) Preliminary 2 C operation mode operation. The 2 C Slave mode. When 2002 Microchip Technology Inc. ...
Page 137
... In Receive mode Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc MODE) R-0 R-0 R-0 ...
Page 138
... SSPEN CKP SSPM3 SSPM2 (SSPADD+1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for x = Bit is unknown 2002 Microchip Technology Inc. ...
Page 139
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. PIC18FXX39 2 C MODE) R/W-0 R/W-0 ...
Page 140
... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated START condition. 8. Receive first (high) byte of Address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Preliminary 2002 Microchip Technology Inc. ...
Page 141
... SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 16-9). 2002 Microchip Technology Inc. PIC18FXX39 The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is com- plete ...
Page 142
... PIC18FXX39 2 FIGURE 16- SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS30485A-page 140 Preliminary 2002 Microchip Technology Inc. ...
Page 143
... FIGURE 16- SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2002 Microchip Technology Inc. PIC18FXX39 Preliminary DS30485A-page 141 ...
Page 144
... PIC18FXX39 2 FIGURE 16-10 SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS30485A-page 142 Preliminary 2002 Microchip Technology Inc. ...
Page 145
... FIGURE 16-11 SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2002 Microchip Technology Inc. PIC18FXX39 Preliminary DS30485A-page 143 ...
Page 146
... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode, and clock stretching is controlled by the BF flag 7-bit Slave Transmit mode (see Figure 16-11). Preliminary 2002 Microchip Technology Inc. ...
Page 147
... CKP bit will not violate the minimum high time requirement for SCL (see Figure 16-12). FIGURE 16-12: CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON 2002 Microchip Technology Inc. C master device Master device asserts clock Master device de-asserts clock Preliminary PIC18FXX39 DX-1 DS30485A-page 145 ...
Page 148
... PIC18FXX39 2 FIGURE 16-13 SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS30485A-page 146 Preliminary 2002 Microchip Technology Inc. ...
Page 149
... FIGURE 16-14 SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2002 Microchip Technology Inc. PIC18FXX39 Preliminary DS30485A-page 147 ...
Page 150
... UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 16-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Preliminary Receiving data ACK '0' '1' 2002 Microchip Technology Inc. ...
Page 151
... MSSP BLOCK DIAGRAM (I SDA SDA in SCL SCL in Bus Collision 2002 Microchip Technology Inc. Note: The MSSP Module, when configured in I Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to initiate transmission before the START condition is complete ...
Page 152
... The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a STOP condition by setting the STOP enable bit PEN (SSPCON2<2>). 12. Interrupt is generated once the STOP condition is complete. Preliminary 2002 Microchip Technology Inc. enable bit, SEN ...
Page 153
... Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend low time of clock period, producing the effective frequency. 2002 Microchip Technology Inc. Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
Page 154
... DX-1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count Preliminary 03h 02h 2002 Microchip Technology Inc. ...
Page 155
... FIGURE 16-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL 2002 Microchip Technology Inc. 16.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the con- tents of the buffer are unchanged (the write doesn’t occur) ...
Page 156
... SSPCON2 is disabled until the Repeated START condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here Repeated START Preliminary 1st bit T BRG BRG 2002 Microchip Technology Inc. ...
Page 157
... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 2002 Microchip Technology Inc. PIC18FXX39 16.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
Page 158
... PIC18FXX39 2 FIGURE 16-21 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS30485A-page 156 Preliminary 2002 Microchip Technology Inc. ...
Page 159
... FIGURE 16-22 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2002 Microchip Technology Inc. PIC18FXX39 Preliminary DS30485A-page 157 ...
Page 160
... SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup STOP condition. Preliminary BRG WCOL Status Flag ACKEN automatically cleared Cleared in software BRG 2002 Microchip Technology Inc. ...
Page 161
... BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF 2002 Microchip Technology Inc. 16.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto ...
Page 162
... Repeated START or STOP conditions. SEN cleared automatically because of bus collision. SSP module reset into IDLE state. SSPIF and BCLIF are cleared in software. SSPIF and BCLIF are cleared in software. Preliminary 2002 Microchip Technology Inc. ...
Page 163
... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF 2002 Microchip Technology Inc. SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S ...
Page 164
... SCL pin, the SCL pin is driven low and the Repeated START condition is complete. a data ’0’, Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. T BRG Preliminary Cleared in software '0' '0' T BRG Interrupt cleared in software '0' 2002 Microchip Technology Inc. ...
Page 165
... SCL PEN BCLIF P SSPIF 2002 Microchip Technology Inc. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to ‘0’. After the BRG times out, SDA is sampled ...
Page 166
... PIC18FXX39 NOTES: DS30485A-page 164 Preliminary 2002 Microchip Technology Inc. ...
Page 167
... TRISC<6> must be cleared (= 0), and • bit TRISC<7> must be set (= 1). Register 17-1 shows the Transmit Status and Control Register (TXSTA) and Register 17-2 shows the Receive Status and Control Register (RCSTA). 2002 Microchip Technology Inc. PIC18FXX39 Preliminary DS30485A-page 165 ...
Page 168
... Value at POR DS30485A-page 166 R/W-0 R/W-0 U-0 TX9 TXEN SYNC — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown 2002 Microchip Technology Inc. ...
Page 169
... Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be Address/Data bit or a parity bit, and must be calculated by user firmware Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 170
... OSC BRGH = 1 (High Speed) Baud Rate = F /(16(X+1)) OSC N/A Value on Value on Bit 0 All Other POR, BOR RESETS TX9D 0000 -010 0000 -010 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 2002 Microchip Technology Inc. ...
Page 171
... HIGH 1000 - 0 894.89 LOW 3.91 - 255 3.50 2002 Microchip Technology Inc. 33 MHz 25 MHz SPBRG value % % (decimal) ERROR KBAUD ERROR +0.39 106 77 ...
Page 172
... MHz SPBRG SPBRG value value % (decimal) (decimal) KBAUD ERROR - 1. 2. 9.90 +3. 19.80 +3. 79.20 +3. 79. 255 0.31 - 255 32.768 kHz SPBRG SPBRG value value % (decimal) (decimal) KBAUD ERROR 51 0.26 -14. 0. 255 0.002 - 255 2002 Microchip Technology Inc. ...
Page 173
... 300 500 HIGH 250 - 0 LOW 0.98 - 255 2002 Microchip Technology Inc. 33 MHz 25 MHz SPBRG value % (decimal) ERROR KBAUD ERROR 9.60 -0.07 214 9.59 -0.15 19.28 +0.39 106 19.30 +0.47 76.39 -0. ...
Page 174
... TXREG. The flag bit becomes valid in the second instruction instruction. Data Bus TXREG Register 8 MSb LSb (8) • • • 0 TSR Register TRMT TX9 TX9D Preliminary cycle following the load Pin Buffer and Control RC6/TX/CK pin SPEN 2002 Microchip Technology Inc. ...
Page 175
... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear. 2002 Microchip Technology Inc. bit 0 bit 1 Word 1 bit 0 ...
Page 176
... ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. CREN OERR ÷ 64 RSR Register MSb or ÷ STOP (8) • • • RX9 Data Recovery RX9D RCREG Register Interrupt RCIF RCIE Preliminary FERR LSb 0 1 START FIFO 8 Data Bus 2002 Microchip Technology Inc. ...
Page 177
... Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear. 2002 Microchip Technology Inc. START bit7/8 STOP bit7/8 STOP ...
Page 178
... RESETS RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2002 Microchip Technology Inc. ...
Page 179
... Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words. FIGURE 17-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit 2002 Microchip Technology Inc bit 1 bit 2 bit 7 bit 0 Word 1 bit0 bit2 bit1 ...
Page 180
... Preliminary Value on Value on Bit 0 All Other POR, BOR RESETS RBIF 0000 000x 0000 000u RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 bit6 bit7 '0' 2002 Microchip Technology Inc. ...
Page 181
... Shaded cells are not used for Synchronous Slave Transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear. 2002 Microchip Technology Inc. To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by set- ting bits SYNC and SPEN and clearing bit CSRC ...
Page 182
... SYNC — BRGH TRMT Preliminary Value on Value on Bit 0 All Other POR, BOR RESETS RBIF 0000 000x 0000 000u RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2002 Microchip Technology Inc. ...
Page 183
... A/D converter module is shut-off and consumes no operating current Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. The A/D module has four registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • ...
Page 184
... Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit 0 AN1 AN0 REF REF AN3 AN3 AN3 — — AN3 AN2 AN3 AN3 AN2 AN3 AN2 AN3 AN2 AN3 AN2 Bit is unknown 2002 Microchip Technology Inc. ...
Page 185
... Voltage V REF * These channels are implemented only on the PIC18F4X39 devices. 2002 Microchip Technology Inc. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion ...
Page 186
... When the conversion is started, the hold- ing capacitor is disconnected from the input pin Sampling Switch ≤ LEAKAGE V = 0.6V T ± 500 Preliminary . A minimum wait must be allowed HOLD ) and the internal sampling S . The sampling HOLD 120 pF HOLD Sampling Switch (kΩ) 2002 Microchip Technology Inc. ...
Page 187
... SS S -120 pF (1 kΩ kΩ + 2.5 kΩ) ln(0.0004883) -120 pF (10.5 kΩ) ln(0.0004883) -1.26 µs (-7.6246) 9.61 µs 2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C ACQ 11.61 µs + 1.25 µs 12.86 µs 2002 Microchip Technology Inc. time, (-Tc HOLD ln(1/2048) ...
Page 188
... MHz 000 2.50 MHz 100 5.00 MHz 001 10.00 MHz 101 20.00 MHz 010 40.00 MHz 110 — 011 Preliminary will be converted PIC18LFXX39 666 kHz 1.33 MHz 2.67 MHz 5.33 MHz 10.67 MHz 21.33 MHz — 2002 Microchip Technology Inc. ...
Page 189
... ADRESH ADRESL 10-bit Result Right Justified 2002 Microchip Technology Inc. (or the last value written to the ADRESH:ADRESL reg- isters). After the A/D conversion is aborted required before the next acquisition is started. After this 2 T wait, acquisition on the selected channel is AD automatically started. The GO/DONE bit can then be set to start the conversion ...
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... ADON 0000 00-0 0000 00-0 PCFG0 ---- -000 ---- -000 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 RE0 ---- -000 ---- -000 LATE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 2002 Microchip Technology Inc. ...
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... The “trip point” voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the 2002 Microchip Technology Inc. The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be “turned off” ...
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... Typical LVDIN (Figure 19-3). This gives users flexibility, because it allows them to configure the Low Voltage Detect interrupt to occur at any voltage in the valid operating range VxEN BODEN EN Preliminary LVDIF LVD Control Register LVDEN – LVD + BGAP 2002 Microchip Technology Inc. ...
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... Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. U-0 R-0 R/W-0 R/W-0 — IRVST LVDEN LVDL3 W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 194
... Figure 19-4 shows typical waveforms that the LVD module may be used to detect. LVDIF may not be set T IVRST T IVRST LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists Preliminary 2002 Microchip Technology Inc. V LVD LVDIF cleared in software V LVD ...
Page 195
... The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. 2002 Microchip Technology Inc. PIC18FXX39 19.3 Operation During SLEEP When enabled, the LVD circuitry continues to operate during SLEEP ...
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... PIC18FXX39 NOTES: DS30485A-page 194 Preliminary 2002 Microchip Technology Inc. ...
Page 197
... The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options. 2002 Microchip Technology Inc. PIC18FXX39 20.1 Configuration Bits The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations ...
Page 198
... STVREN 1--- -1-1 CP1 CP0 ---- 1111 — — 11-- ---- WRT1 WRT0 ---- 1111 — — 111- ---- EBTR1 EBTR0 ---- 1111 — — -1-- ---- REV1 REV0 (2) DEV4 DEV3 0000 0100 R/P-0 R/P-1 R/P-0 FOSC2 FOSC1 FOSC0 bit 0 ) OSC 2002 Microchip Technology Inc. ...
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... WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend Readable bit - n = Value when device is unprogrammed 2002 Microchip Technology Inc. U-0 U-0 U-0 R/P-1 — — — BORV1 P = Programmable bit U = Unimplemented bit, read as ‘ ...
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... Legend Readable bit - n = Value when device is unprogrammed DS30485A-page 198 U-0 U-0 U-0 U-0 — — — — Clearable bit U = Unimplemented bit, read as ‘0’ Unchanged from programmed state Preliminary R/P-1 U-0 R/P-1 LVP — STVREN bit 0 2002 Microchip Technology Inc. ...