PIC18F4539T-E/ML Microchip Technology, PIC18F4539T-E/ML Datasheet - Page 162

• Manufacturer Part Number: PIC18F4539T-E/ML
• Description: IC PIC MCU FLASH 12KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4539T-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18FXX39
16.4.17.1
During a START condition, a bus collision occurs if:
a)
b)
During a START condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted,
• the BCLIF flag is set, and
• the MSSP module is reset to its IDLE state
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 16-26:
DS30485A-page 160
(Figure 16-26).
SDA
SCL
SEN
BCLIF
S
SSPIF
SDA or SCL are sampled low at the beginning of
the START condition (Figure 16-26).
SCL is sampled low before SDA is asserted low
(Figure 16-27).
Bus Collision During a START
Condition
BUS COLLISION DURING START CONDITION (SDA ONLY)
condition if SDA = 1, SCL = 1
Set SEN, enable START
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
Preliminary
SSPIF and BCLIF are
cleared in software.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 16-28). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to ‘0’, and during this time, if the SCL pins
are sampled as '0', a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.
Note:
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
The reason that bus collision is not a factor
during a START condition, is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
SSPIF and BCLIF are
cleared in software.
 2002 Microchip Technology Inc.