PIC18F4539T-E/ML Microchip Technology, PIC18F4539T-E/ML Datasheet - Page 155

• Manufacturer Part Number: PIC18F4539T-E/ML
• Description: IC PIC MCU FLASH 12KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4539T-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4.8
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (T
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the START condition
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (T
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended,
leaving the SDA line held low and the START condition
is complete.
FIGURE 16-19:
 2002 Microchip Technology Inc.
Note:
If at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF is set, the START condition is
aborted, and the I
IDLE state.
I
CONDITION TIMING
2
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
2
C module is reset into its
SDA
SCL
BRG
BRG
SDA = 1,
SCL = 1
T
), the
), the
BRG
Preliminary
Set S bit (SSPSTAT<3>)
T
S
BRG
At completion of START bit,
Hardware clears SEN bit
16.4.8.1
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
and sets SSPIF bit
Note:
T
Write to SSPBUF occurs here
BRG
1st bit
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
WCOL Status Flag
T
BRG
PIC18FXX39
2nd bit
DS30485A-page 153