AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 109

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16. MultiMedia Card Controller
16.1
16.1.1
16.1.2
16.2
4109L–8051–02/08
Card Concept
Bus Concept
Card Signals
Card Registers
The AT8xC51SND1C implements a MultiMedia Card (MMC) controller. The MMC is used to
store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or
removed from the application.
The basic MultiMedia Card concept is based on transferring data via a minimum number of
signals.
The communication signals are:
•
•
•
Within the card interface five registers are defined: OCR, CID, CSD, RCA and DSR. These can
be accessed only by the corresponding commands.
The 32-bit Operation Conditions Register (OCR) stores the V
register is optional and can be read only.
The 128-bit wide CID register carries the card identification information (Card ID) used during
the card identification procedure.
The 128-bit wide Card-Specific Data register (CSD) provides information on how to access the
card contents. The CSD defines the data format, error correction type, maximum data access
time, data transfer speed, and whether the DSR register can be used.
The 16-bit Relative Card Address register (RCA) carries the card address assigned by the host
during the card identification. This address is used for the addressed host-card communication
after the card identification procedure.
The 16-bit Driver Stage Register (DSR) can be optionally used to improve the bus performance
for extended operating conditions (depending on parameters like bus length, transfer rate or
number of cards).
The MultiMedia Card bus is designed to connect either solid-state mass-storage memory or I/O-
devices in a card format to multimedia applications. The bus implementation allows the cover-
age of application fields from low-cost systems to systems with a fast data transfer rate. It is a
single master bus with a variable number of slaves. The MultiMedia Card bus master is the bus
controller and each slave is either a single mass storage card (with possibly different technolo-
gies such as ROM, OTP, Flash etc.) or an I/O-card with its own controlling unit (on card) to
perform the data transfer.
The MultiMedia Card bus also includes power connections to supply the cards.
CLK: with each cycle of this signal a one bit transfer on the command and data lines is done.
The frequency may vary from zero to the maximum clock frequency.
CMD: is a bi-directional command channel used for card initialization and data transfer
commands. The CMD signal has 2 operation modes: open-drain for initialization mode and
push-pull for fast command transfer. Commands are sent from the MultiMedia Card bus
master to the card and responses from the cards to the host.
DAT: is a bi-directional data channel. The DAT signal operates in push-pull mode. Only one
card or the host is driving this signal at a time.
DD
voltage profile of the card. The
AT8xC51SND1C
109