AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 50

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3
10.3.1
10.3.2
10.4
50
Idle Mode
Power-down Mode
AT8xC51SND1C
Entering Idle Mode
Exiting Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode, pro-
gram execution halts. Idle mode freezes the clock to the CPU at known states while the
peripherals continue to be clocked (refer to section “Oscillator”, page 13). The CPU status
before entering Idle mode is preserved, i.e., the program counter and program status word reg-
ister retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also
retained. The status of the Port pins during Idle mode is detailed in
To enter Idle mode, the user must set the IDL bit in PCON register (see Table 60). The
AT8xC51SND1C enters Idle mode upon execution of the instruction that sets IDL bit. The
instruction that sets IDL bit is the last instruction executed.
Note:
There are 2 ways to exit Idle mode:
1. Generate an enabled interrupt.
2. Generate a reset.
Note:
The Power-down mode places the AT8xC51SND1C in a very low power state. Power-down
mode stops the oscillator and freezes all clocks at known states (refer to the Section "Oscillator",
page 13). The CPU status prior to entering Power-down mode is preserved, i.e., the program
counter, program status word register retain their data for the duration of Power-down mode. In
addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-
down mode is detailed in
Note:
–
–
If IDL bit and PD bit are set simultaneously, the AT8xC51SND1C enter Power-down mode. Then it
does not go in Idle mode when exiting Power-down mode.
Hardware clears IDL bit in PCON register which restores the clock to the CPU.
Execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Idle mode. The general-purpose
flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt
occurred during normal operation or during Idle mode. When Idle mode is exited by
an interrupt, the interrupt service routine may examine GF1 and GF0.
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution momentarily
resumes with the instruction immediately following the instruction that activated the
Idle mode and may continue for a number of clock cycles before the internal reset
algorithm takes control. Reset initializes the AT8xC51SND1C and vectors the CPU
to address C:0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-
sible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction
immediately following the instruction that activated Idle mode should not write to a Port pin or to
the external RAM.
V
tion. Notice, however, that V
DD
may be reduced to as low as V
Table
58.
DD
is not reduced until Power-down mode is invoked.
RET
during Power-down mode to further reduce power dissipa-
Table
58.
4109L–8051–02/08