AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 160

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.1.2
20.1.3
160
AT8xC51SND1C
Master Transmitter Mode
Master Receiver Mode
Table 136. Serial Clock Rates
Note:
In the master transmitter mode, a number of data Bytes are transmitted to a slave receiver (see
Figure 20-3). Before the master transmitter mode can be entered, SSCON must be initialized as
follows:
SSCR2:0 define the serial bit rate (see Table 136). SSPE must be set to enable the controller.
SSSTA, SSSTO and SSI must be cleared.
The master transmitter mode may now be entered by setting the SSSTA bit. The TWI logic will
now monitor the TWI bus and generate a START condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SSI bit in SSCON) is set, and
the status code in SSSTA is 08h. This status must be used to vector to an interrupt routine that
loads SSDAT with the slave address and the data direction bit (SLA+W). The serial interrupt flag
(SSI) must then be cleared before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowledgment bit
has been received, SSI is set again and a number of status code in SSSTA are possible. There
are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was
enabled (SSAA = logic 1). The appropriate action to be taken for each of these status code is
detailed in Table 137. This scheme is repeated until a STOP condition is transmitted.
SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in Table 137.
After a repeated START condition (state 10h) the controller may switch to the master receiver
mode by loading SSDAT with SLA+R.
In the master receiver mode, a number of data Bytes are received from a slave transmitter (see
Figure 20-4). The transfer is initialized as in the master transmitter mode. When the START con-
dition has been transmitted, the interrupt routine must load SSDAT with the 7 - bit slave address
and the data direction bit (SLA+R). The serial interrupt flag (SSI) must then be cleared before
the serial transfer can continue.
1. These bit rates are outside of the low speed standard specification limited to 100 kHz but can
2
0
0
0
0
1
1
1
1
Bit Rate
SSCR2
SSCRx
be used with high speed TWI components limited to 400 kHz.
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0.5 < ⋅ < 125
SSPE
F
PER
1
200
53.5
62.5
12.5
100
= 6 MHz
47
75
(1)
(1)
SSSTA
Bit Frequency (kHz)
0
0.67 < ⋅ < 166.7
F
PER
133.3
266.7
62.5
71.5
16.5
100
= 8 MHz
83
SSSTO
(1)
(1)
0
(1)
0.81 < ⋅ < 208.3
F
PER
104.2
166.7
333.3
SSI
78.125
125
20.83
0
= 10 MHz
89.3
(1)
(1)
(1)
(1)
(1)
SSAA
X
96 ⋅ (256 – reload value Timer 1)
F
PER
Bit Rate
SSCR1
Divided By
128
112
480
96
80
60
30
4109L–8051–02/08
Bit Rate
SSCR0