AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 30

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.3.2
30
AT8xC51SND1C
Application
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses
83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see
Table 22) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see
Figure 6).
Figure 6. Dual Data Pointer Implementation
Software can take advantage of the additional data pointers to both increase speed and reduce
code size, for example, block operations (copy, compare, search …) are well served by using
one data pointer as a “source” pointer and the other one as a “destination” pointer.
Below is an example of block move implementation using the 2 pointers and coded in assem-
bler. The latest C compiler also takes advantage of this feature by providing enhanced algorithm
libraries.
The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in
the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to
a particular state, but simply toggles it. In simple routines, such as the block move example, only
the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words,
the block move routine works the same whether DPS is '0' or '1' on entry.
; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added
AUXR1
move:
mv_loop: inc
end_move:
EQU
mov
inc
mov
movx A,@DPTR
inc
inc
movx @DPTR,A
inc
jnz
DPTR1
0A2h
DPTR,#SOURCE ; address of SOURCE
AUXR1
DPTR,#DEST
AUXR1
DPTR
AUXR1
DPTR
mv_loop
DPTR0
; switch data pointers
; address of DEST
; switch data pointers
; get a Byte from SOURCE
; increment SOURCE address
; switch data pointers
; write the Byte to DEST
; increment DEST address
; check for NULL terminator
DPH0
DPH1
DPL0
DPL1
DPS
0
1
0
1
AUXR1.0
DPH
DPL
DPTR
4109L–8051–02/08