LH7A404N0F000B1A Sharp Microelectronics, LH7A404N0F000B1A Datasheet - Page 23

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LH7A404N0F000B1A

Manufacturer Part Number
LH7A404N0F000B1A
Description
IC ARM9 BLUESTREAK MCU 324CABGA
Manufacturer
Sharp Microelectronics
Series
BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B1A

Core Processor
ARM9
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-CABGA
For Use With
568-4304 - BOARD EVAL FOR LH7A404
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
425-2497

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH7A404N0F000B1A
Manufacturer:
Sharp Microelectronics
Quantity:
10 000
32-Bit System-on-Chip
Embedded SRAM
SRAM. This embedded memory is used for storing
code, data, or LCD frame data and is contiguous with
external SDRAM. The 80KB is large enough to store a
QVGA frame (320 × 240) at 8 bits per pixel, equivalent
to 70KB of information.
power consumed by LH7A404 applications. Normally,
the system performs external accesses to acquire this
data. The LCD controller automatically uses an over-
flow frame buffer in SDRAM if a larger screen size is
required. This overflow buffer can be located on any
4KB page boundary in SDRAM, allowing software to
set the MMU (in the LCD controller) page tables so the
two memory areas appear contiguous, allowing byte,
half-word, and word accesses.
Static Memory Controller (SMC)
provides an interface between the AMBA AHB system
bus and external (off-chip) memory devices.
pendently configurable memory banks. Each memory
bank can support:
• SRAM
• ROM
• Flash EPROM
• Burst ROM memory.
16-, or 32-bit external memory data paths. The memory
controller can be configured to support either little-
endian or big-endian operation.
• Non-burst read and write accesses only to high-
• Non-burst write accesses, nonburst read accesses
• Memory bank select
• Access sequencing
• Wait state generation
• Byte lane write control
• External bus interface
• CompactFlash or PCMCIA interfacing.
Data Sheet
speed CMOS static RAM
and asynchronous page mode read accesses to
fast-boot block flash memory.
The LH7A404 incorporates 80KB of embedded
Locating the frame buffer on chip reduces the overall
The asynchronous Static Memory Controller (SMC)
The SMC simultaneously supports up to eight inde-
Each memory bank may use devices with either 8-,
The memory banks can be configured to support:
The SMC has six main functions:
Version 1.0
SDRAM (Synchronous) Memory Controller
vides a high speed memory interface to a wide variety of
synchronous memory devices, including Synchronous
DRAM, Synchronous Flash and Synchronous ROMs.
• LCD DMA port for high bandwidth
• Up to four Synchronous Memory banks can be inde-
• Includes special configuration bits for Synchronous
• Includes ability to program Synchronous Flash
• On booting from Synchronous ROM, (and optionally
• Data is transferred between the controller and the
• Programmable for 16- or 32-bit data bus size
• Two reset domains enable Synchronous DRAM con-
• Power saving Synchronous Memory SCKE and
Secure Digital/MultiMediaCard (MMC)
that meets the security, capacity, performance,
and environment requirements inherent in electronic
devices. The SD Memory Card host supports
MultiMediaCard (MMC) operation as well, and is com-
patible with MMC Cards.
card controller or as an SD Card controller, and sup-
ports the full SD/MMC bus protocol as defined in the
MMC system specification 2.11 provided by the MMC
Association and the SD Memory Card Spec v1.0 from
the SD Association.
pendently set up
ROM operation
devices using write and erase commands
with Synchronous Flash), a configuration sequence is
performed before releasing the processor from reset
Synchronous DRAM in four-word bursts. Longer
transfers within the same page are concatenated,
forming a seamless burst
tents to be preserved over a ‘soft’ reset
external clock modes provided.
The SDRAM (Synchronous) Memory Controller pro-
The key features of the controller are:
The SD Memory Card is a flash-based memory card
The SD/MMC controller can be used as an MMC
LH7A404
23

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