LH7A404N0F000B1A Sharp Microelectronics, LH7A404N0F000B1A Datasheet - Page 35

• Manufacturer Part Number: LH7A404N0F000B1A
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B1A

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2497

32-Bit System-on-Chip
AC Specifications (Commercial)
tions following an internal reference clock signal.
The illustration in Figure 7 represents all cases of
these sets of measurement parameters.
• HCLK, internal System Bus clock (‘C’ in timing data)
• PCLK, the Peripheral Bus clock
• SSPCLK, the Synchronous Serial Port clock
• UARTCLK, the UART Interface clock
• LCDDCLK, the LCD Data clock from the
• ACBITCLK, the AC97 and ACI clock
• SCLK, the Synchronous Memory clock.
point of the clock to the 50% point of the signal.
Data Sheet
LCD Controller
All signals described in Table 11 relate to transi-
The reference clock signals in this design are:
All signal transitions are measured from the 50%
REFERENCE
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
CLOCK
Figure 7. LH7A404 Signal Timing
tOVXXX
Version 1.0
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 11.
amount of time the output must be held valid after the
rising edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 11.
amount of setup time the input signal must be valid after
a valid address bus, or rising edge of the peripheral
clock. Maximum requirements for tISXXX are shown in
Table 11.
amount of time the output must be held valid following
the rising edge of the reference clock signal. Minimum
requirements are shown in Table 11.
tISXXX tIHXXX
For outputs from the LH7A404, tOVXXX (e.g. tOVA)
The signal tOHXXX (e.g. tOHA) represents the
For inputs, tISXXX (e.g. tISD) represents the
The signal tIHXXX (e.g. tIHD) represents the
tOHXXX
LH7A404
LH7A404-9
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