LH7A404N0F000B1A Sharp Microelectronics, LH7A404N0F000B1A Datasheet - Page 24

• Manufacturer Part Number: LH7A404N0F000B1A
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B1A

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2497

LH7A404
SD/MMC INTERFACE DESCRIPTION
bus (clock, command, and data) to input and output
data to and from the MMC, and to configure and
acquire status information from the card. The SD con-
troller differs in that it has four data lines instead of one.
groups:
• Power supply: VSS1, VSS2, and VDD
• Data transfer group: MMCCMD, MMCDATA0,
• Clock: MMCCLK
MMC CONTROLLER
tions, serves as the bus master for the MMC Bus and
implements the standard interface to the MMC (card
initialization, CRC generation and validation, com-
mand/response transactions, etc.).
Smart Card Interface (SCI)
Card reader. The SCI can autonomously control data
transfer to and from the Smart Card. Transmit and
receive data FIFOs are provided to reduce the required
interaction between the CPU core and the peripheral.
SCI FEATURES
• Supports asynchronous T0 and T1 transmission
• Supports clock rate conversion factor F = 372, with
• Eight-character-deep buffered Tx and Rx paths
• Direct interrupts for Tx and Rx FIFO level monitoring
• Interrupt status register
• Hardware-initiated card deactivation sequence on
• Software-initiated card deactivation sequence on
• Limited support for synchronous smart cards via reg-
24
MMCDATA1, MMCDATA2, MMCDATA3 (for MMC,
do not use MMCDATA1, MMCDATA2, MMCDATA3)
protocols
bit rate adjustment factors of D = 1, 2, or 4
detection of card removal
transaction complete
istered input/output.
The SD/MMC controller uses the three-wire signal
The SD/MMC bus lines can be divided into three
The MMC controller implements MMC-specific func-
The SCI (ISO7816) connects to an external Smart
Version 1.0
PROGRAMMABLE PARAMETERS
• Smart Card clock frequency
• Communication baud rate
• Protocol convention
• Card activation/deactivation time
• Maximum time for first character of Answer to Reset
• Maximum ATR character stream duration checking
• Maximum time of receipt of first character of data
• Maximum time allowed between characters checking
• Character guard time
• Block guard time
• Transmit/receive character retry.
Direct Memory Access Controller (DMA)
streams from 20 internal peripherals to the system
memory using 10 fully-independent programmable
channels which consist of five M2P (transmit) channels
and five P2M (receive) channels.
channels:
• USB Device
• USB Host
• SD/MMC
• AC97
• UART1
• UART2
• UART3
one Rx channel, except the AC97, which contains three
Tx and Rx channels. These peripherals also have their
own bi-directional DMA bus, capable of simultaneously
transferring data in both directions. All memory trans-
fers take place via the main system AHB bus.
streams from memory-to-memory (M2M) or memory-
to-external peripheral (M2P) using two dedicated
M2M channels. External handshake signals are avail-
able to support memory-to-/from-external peripheral
(M2P/P2M) transfers. A software trigger is available for
M2M transfers only.
(ATR) reception checking
stream checking
The DMA Controller can be used to interface
The following peripherals may be allocated to the 10
Each of the above peripherals contain one Tx and
The DMA Controller can also be used to interface
32-Bit System-on-Chip
Data Sheet